Commit 07622094 authored by Connor Abbott's avatar Connor Abbott

bifrost: Add a few 16-bit-related things

parent ccfed3b8
......@@ -362,9 +362,14 @@ static const FMAOpInfo FMAOpInfos[] = {
{ 0x80000, "FMA.v2f16", FMAThreeSrcFmod16 },
{ 0xc0000, "MAX.v2f16", FMATwoSrcFmod16 },
{ 0xc4000, "MIN.v2f16", FMATwoSrcFmod16 },
{ 0xc8000, "FCMP.GL", FMAFcmp16 },
{ 0xcc000, "FCMP.D3D", FMAFcmp16 },
{ 0xcf900, "ADD.v2i16", FMATwoSrc },
{ 0xcfc10, "ADDC.i32", FMATwoSrc },
{ 0xcfd80, "ADD.i32.i16.X", FMATwoSrc },
{ 0xcfd90, "ADD.i32.u16.X", FMATwoSrc },
{ 0xcfdc0, "ADD.i32.i16.Y", FMATwoSrc },
{ 0xcfdd0, "ADD.i32.u16.Y", FMATwoSrc },
{ 0xd8000, "ADD.v2f16", FMATwoSrcFmod16 },
{ 0xdc000, "CSEL.FEQ.v2f16", FMAFourSrc },
{ 0xdc200, "CSEL.FGT.v2f16", FMAFourSrc },
......@@ -375,10 +380,22 @@ static const FMAOpInfo FMAOpInfos[] = {
{ 0xdcc00, "CSEL.UGT.v2i16", FMAFourSrc },
{ 0xdce00, "CSEL.UGE.v2i16", FMAFourSrc },
{ 0xdd000, "F32_TO_F16", FMATwoSrc },
{ 0xe0056, "F16_TO_I16", FMAOneSrc },
{ 0xe0057, "F16_TO_U16", FMAOneSrc },
{ 0xe00d0, "I16_TO_F16", FMAOneSrc },
{ 0xe00d1, "U16_TO_F16", FMAOneSrc },
{ 0xe0046, "F16_TO_I16.XX", FMAOneSrc },
{ 0xe0047, "F16_TO_U16.XX", FMAOneSrc },
{ 0xe004e, "F16_TO_I16.YX", FMAOneSrc },
{ 0xe004f, "F16_TO_U16.YX", FMAOneSrc },
{ 0xe0056, "F16_TO_I16.XY", FMAOneSrc },
{ 0xe0057, "F16_TO_U16.XY", FMAOneSrc },
{ 0xe005e, "F16_TO_I16.YY", FMAOneSrc },
{ 0xe005f, "F16_TO_U16.YY", FMAOneSrc },
{ 0xe00c0, "I16_TO_F16.XX", FMAOneSrc },
{ 0xe00c1, "U16_TO_F16.XX", FMAOneSrc },
{ 0xe00c8, "I16_TO_F16.YX", FMAOneSrc },
{ 0xe00c9, "U16_TO_F16.YX", FMAOneSrc },
{ 0xe00d0, "I16_TO_F16.XY", FMAOneSrc },
{ 0xe00d1, "U16_TO_F16.XY", FMAOneSrc },
{ 0xe00d8, "I16_TO_F16.YY", FMAOneSrc },
{ 0xe00d9, "U16_TO_F16.YY", FMAOneSrc },
{ 0xe0136, "F32_TO_I32", FMAOneSrc },
{ 0xe0137, "F32_TO_U32", FMAOneSrc },
{ 0xe0178, "I32_TO_F32", FMAOneSrc },
......@@ -395,6 +412,7 @@ static const FMAOpInfo FMAOpInfos[] = {
{ 0xe01a3, "F16_TO_F32.Y", FMAOneSrc },
{ 0xe032c, "NOP", FMAOneSrc },
{ 0xe032d, "MOV", FMAOneSrc },
{ 0xe032f, "SWZ.YY.v2i16", FMAOneSrc },
// From the ARM patent US20160364209A1:
// "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
// and x1 is a floating point value in a predetermined range where the
......@@ -424,8 +442,8 @@ static const FMAOpInfo FMAOpInfos[] = {
// ADD_HIGH32 in the ADD slot to do 64-bit addition).
{ 0xe1cc0, "ADD_LOW32", FMATwoSrc },
{ 0xe1e00, "SEL.XX.i16", FMATwoSrc },
{ 0xe1e10, "SEL.XY.i16", FMATwoSrc },
{ 0xe1e08, "SEL.YX.i16", FMATwoSrc },
{ 0xe1e10, "SEL.XY.i16", FMATwoSrc },
{ 0xe1e18, "SEL.YY.i16", FMATwoSrc },
{ 0xe7800, "IMAD", FMAThreeSrc },
{ 0xe78db, "POPCNT", FMAOneSrc },
......@@ -755,8 +773,14 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x07000, "FCMP.D3D", ADDFcmp },
{ 0x07856, "F16_TO_I16", ADDOneSrc },
{ 0x07857, "F16_TO_U16", ADDOneSrc },
{ 0x078d0, "I16_TO_F16", ADDOneSrc },
{ 0x078d1, "U16_TO_F16", ADDOneSrc },
{ 0x078c0, "I16_TO_F16.XX", ADDOneSrc },
{ 0x078c1, "U16_TO_F16.XX", ADDOneSrc },
{ 0x078c8, "I16_TO_F16.YX", ADDOneSrc },
{ 0x078c9, "U16_TO_F16.YX", ADDOneSrc },
{ 0x078d0, "I16_TO_F16.XY", ADDOneSrc },
{ 0x078d1, "U16_TO_F16.XY", ADDOneSrc },
{ 0x078d8, "I16_TO_F16.YY", ADDOneSrc },
{ 0x078d9, "U16_TO_F16.YY", ADDOneSrc },
{ 0x07936, "F32_TO_I32", ADDOneSrc },
{ 0x07937, "F32_TO_U32", ADDOneSrc },
{ 0x07978, "I32_TO_F32", ADDOneSrc },
......@@ -773,8 +797,13 @@ static const ADDOpInfo ADDOpInfos[] = {
{ 0x079a2, "F16_TO_F32.X", ADDOneSrc },
// take the high 16 bits, ...
{ 0x079a3, "F16_TO_F32.Y", ADDOneSrc },
{ 0x07b2b, "SWZ.YX.v2i16", ADDOneSrc },
{ 0x07b2c, "NOP", ADDOneSrc },
{ 0x07b29, "SWZ.XX.v2i16", ADDOneSrc },
// Logically, this should be SWZ.XY, but that's equivalent to a move, and
// this seems to be the canonical way the blob generates a MOV.
{ 0x07b2d, "MOV", ADDOneSrc },
{ 0x07b2f, "SWZ.YY.v2i16", ADDOneSrc },
{ 0x07b8d, "FRCP_EXP", ADDOneSrc },
// From the ARM patent US20160364209A1:
// "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
......@@ -1148,7 +1177,7 @@ static void DumpADD(uint64_t word, Regs regs, Regs nextRegs, uint64_t *consts, u
else
printf("samp:%d ", samplerIndex);
}
// fallthrough
break;
}
case ADDVaryingInterp: {
if (ADD.op & 0x200)
......
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