From ebd455e5d10a1355f30819068f1a9fc52d3b8e72 Mon Sep 17 00:00:00 2001
From: Lucas De Marchi <lucas.demarchi@intel.com>
Date: Wed, 1 Mar 2023 17:34:09 -0800
Subject: [PATCH] drm/xe/display: Move device info initialization to display
Instead of initializing the display info together with the platform in
xe_pci.c, let the display part initialize it. The small disadvantage is
that the description struct is not automatically mapped from the PCI ID,
but just doing a switch on the platform, that should already be set
during display initialization should be ok.
This allows to encapsulate the display details inside the display
compilation units.
Also use __diag_push() / __diag_pop() like in xe_step to handle the few
places where -Woverride-init should be disabled.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://lore.kernel.org/r/20230302013411.3262608-6-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/Makefile | 3 -
drivers/gpu/drm/xe/xe_display.c | 128 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_display.h | 15 ++--
drivers/gpu/drm/xe/xe_pci.c | 98 ++----------------------
4 files changed, 142 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 0d12bca010de0..f34d4bdd510b6 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -24,9 +24,6 @@ subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides)
subdir-ccflags-y += $(call cc-disable-warning, frame-address)
subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
-# Fine grained warnings disable
-CFLAGS_xe_pci.o = $(call cc-disable-warning, override-init)
-
subdir-ccflags-y += -I$(obj) -I$(srctree)/$(src)
# generated sources
diff --git a/drivers/gpu/drm/xe/xe_display.c b/drivers/gpu/drm/xe/xe_display.c
index afff26c580156..52935e5b72f87 100644
--- a/drivers/gpu/drm/xe/xe_display.c
+++ b/drivers/gpu/drm/xe/xe_display.c
@@ -10,6 +10,7 @@
#include <linux/fb.h>
+#include <drm/drm_drv.h>
#include <drm/drm_managed.h>
#include <drm/xe_drm.h>
@@ -392,4 +393,131 @@ void xe_display_pm_resume(struct xe_device *xe)
intel_power_domains_enable(xe);
}
+/* Display info initialization */
+__diag_push();
+__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
+
+#define __DISPLAY_DEFAULTS \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | \
+ BIT(PIPE_C) | BIT(PIPE_D), \
+ .cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
+ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }
+
+#define GEN12_DISPLAY \
+ __DISPLAY_DEFAULTS, \
+ .ver = 12, \
+ .abox_mask = GENMASK(2, 1), \
+ .has_dmc = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 0, /* FIXME: LUT load is broken with huge DSB */ \
+ .dbuf.size = 2048, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+ .has_dsc = 1, \
+ .fbc_mask = BIT(INTEL_FBC_A), \
+ .has_fpga_dbg = 1, \
+ .has_hdcp = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .has_psr_hw_tracking = 1, \
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
+
+#define GEN13_DISPLAY \
+ __DISPLAY_DEFAULTS, \
+ .ver = 13, \
+ .abox_mask = GENMASK(1, 0), \
+ .color = { \
+ .degamma_lut_size = 128, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ }, \
+ .dbuf.size = 4096, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
+ BIT(DBUF_S4), \
+ .has_dmc = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_dsc = 1, \
+ .fbc_mask = BIT(INTEL_FBC_A), \
+ .has_fpga_dbg = 1, \
+ .has_hdcp = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1
+
+void xe_display_info_init(struct xe_device *xe)
+{
+ if (!xe->info.enable_display)
+ return;
+
+ switch (xe->info.platform) {
+ case XE_TIGERLAKE:
+ case XE_DG1:
+ xe->info.display = (struct xe_device_display_info) { GEN12_DISPLAY };
+ break;
+ case XE_ROCKETLAKE:
+ xe->info.display = (struct xe_device_display_info) {
+ GEN12_DISPLAY,
+ .abox_mask = BIT(0),
+ .has_hti = 1,
+ .has_psr_hw_tracking = 0,
+ .cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C),
+ .pipe_mask =
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ };
+ break;
+ case XE_ALDERLAKE_S:
+ case XE_ALDERLAKE_P:
+ case XE_ALDERLAKE_N:
+ xe->info.display = (struct xe_device_display_info) {
+ GEN12_DISPLAY,
+ .has_hti = 1,
+ .has_psr_hw_tracking = 0,
+ };
+ break;
+ case XE_DG2:
+ xe->info.display = (struct xe_device_display_info) {
+ GEN13_DISPLAY,
+ .cpu_transcoder_mask =
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+ };
+ break;
+ case XE_METEORLAKE:
+ xe->info.display = (struct xe_device_display_info) {
+ GEN13_DISPLAY,
+ .ver = 14,
+ .has_cdclk_crawl = 1,
+ .has_cdclk_squash = 1,
+ };
+ break;
+ default:
+ /*
+ * If platform doesn't have display, enable_display should
+ * had been forced to false already at this point
+ */
+ drm_WARN_ON(&xe->drm, 1);
+ }
+}
+
+__diag_pop();
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_display.h b/drivers/gpu/drm/xe/xe_display.h
index e5ddbf4a57d29..84c556111c918 100644
--- a/drivers/gpu/drm/xe/xe_display.h
+++ b/drivers/gpu/drm/xe/xe_display.h
@@ -6,16 +6,18 @@
#ifndef _XE_DISPLAY_H_
#define _XE_DISPLAY_H_
-#include <drm/drm_drv.h>
-
#include "xe_device.h"
+struct drm_driver;
+
#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
int xe_display_set_driver_hooks(struct pci_dev *pdev, struct drm_driver *driver);
int xe_display_create(struct xe_device *xe);
+void xe_display_info_init(struct xe_device *xe);
+
int xe_display_init_nommio(struct xe_device *xe);
void xe_display_fini_nommio(struct drm_device *dev, void *dummy);
@@ -51,6 +53,8 @@ xe_display_set_driver_hooks(struct pci_dev *pdev, struct drm_driver *driver) { r
static inline int
xe_display_create(struct xe_device *xe) { return 0; }
+static inline void xe_display_info_init(struct xe_device *xe) { }
+
static inline int
xe_display_enable(struct pci_dev *pdev, struct drm_driver *driver) { return 0; }
@@ -58,12 +62,7 @@ static inline int
xe_display_init_nommio(struct xe_device *xe) { return 0; }
static inline void xe_display_fini_nommio(struct drm_device *dev, void *dummy) {}
-static inline int xe_display_init_noirq(struct xe_device *xe)
-{
- if (xe->info.display.pipe_mask != 0)
- drm_warn(&xe->drm, "CONFIG_DRM_XE_DISPLAY is unset, but device is display capable\n");
- return 0;
-}
+static inline int xe_display_init_noirq(struct xe_device *xe) { return 0; }
static inline void
xe_display_fini_noirq(struct drm_device *dev, void *dummy) {}
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 521c776dc266f..12701ca0584d4 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -17,6 +17,7 @@
#include "regs/xe_regs.h"
#include "regs/xe_gt_regs.h"
#include "xe_device.h"
+#include "xe_display.h"
#include "xe_drv.h"
#include "xe_gt.h"
#include "xe_macros.h"
@@ -51,8 +52,6 @@ struct xe_device_desc {
u8 require_force_probe:1;
u8 is_dgfx:1;
- struct xe_device_display_info display;
-
/*
* FIXME: Xe doesn't care about presence/lack of 4tile since we can
* already determine that from the graphics IP version. This flag
@@ -62,6 +61,9 @@ struct xe_device_desc {
u8 has_llc:1;
};
+__diag_push();
+__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
+
#define PLATFORM(x) \
.platform = (x), \
.platform_name = #x
@@ -173,77 +175,9 @@ static const struct xe_media_desc media_xelpmp = {
BIT(XE_HW_ENGINE_VECS0), /* TODO: add GSC0 */
};
-#define __DISPLAY_DEFAULTS \
- .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .cpu_transcoder_mask = \
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
- BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .pipe_offsets = { \
- [TRANSCODER_A] = PIPE_A_OFFSET, \
- [TRANSCODER_B] = PIPE_B_OFFSET, \
- [TRANSCODER_C] = PIPE_C_OFFSET, \
- [TRANSCODER_D] = PIPE_D_OFFSET, \
- [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
- }, \
- .trans_offsets = { \
- [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
- [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
- [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
- [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
- [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
- [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- }, \
-
-#define GEN12_DISPLAY \
- .display = (struct xe_device_display_info){ \
- __DISPLAY_DEFAULTS \
- .ver = 12, \
- .abox_mask = GENMASK(2, 1), \
- .has_dmc = 1, \
- .has_dp_mst = 1, \
- .has_dsb = 0, /* FIXME: LUT load is broken with huge DSB */ \
- .dbuf.size = 2048, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
- .has_dsc = 1, \
- .fbc_mask = BIT(INTEL_FBC_A), \
- .has_fpga_dbg = 1, \
- .has_hdcp = 1, \
- .has_ipc = 1, \
- .has_psr = 1, \
- .has_psr_hw_tracking = 1, \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
- }
-
-#define GEN13_DISPLAY \
- .display = (struct xe_device_display_info){ \
- __DISPLAY_DEFAULTS \
- .ver = 13, \
- .abox_mask = GENMASK(1, 0), \
- .color = { \
- .degamma_lut_size = 128, .gamma_lut_size = 1024, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- }, \
- .dbuf.size = 4096, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
- BIT(DBUF_S4), \
- .has_dmc = 1, \
- .has_dp_mst = 1, \
- .has_dsb = 1, \
- .has_dsc = 1, \
- .fbc_mask = BIT(INTEL_FBC_A), \
- .has_fpga_dbg = 1, \
- .has_hdcp = 1, \
- .has_ipc = 1, \
- .has_psr = 1, \
- }
-
static const struct xe_device_desc tgl_desc = {
.graphics = &graphics_xelp,
.media = &media_xem,
- GEN12_DISPLAY,
PLATFORM(XE_TIGERLAKE),
.has_llc = 1,
.require_force_probe = true,
@@ -252,9 +186,6 @@ static const struct xe_device_desc tgl_desc = {
static const struct xe_device_desc rkl_desc = {
.graphics = &graphics_xelp,
.media = &media_xem,
- GEN12_DISPLAY,
- .display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
PLATFORM(XE_ROCKETLAKE),
.require_force_probe = true,
};
@@ -262,9 +193,6 @@ static const struct xe_device_desc rkl_desc = {
static const struct xe_device_desc adl_s_desc = {
.graphics = &graphics_xelp,
.media = &media_xem,
- GEN12_DISPLAY,
- .display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
PLATFORM(XE_ALDERLAKE_S),
.has_llc = 1,
.require_force_probe = true,
@@ -275,9 +203,6 @@ static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
static const struct xe_device_desc adl_p_desc = {
.graphics = &graphics_xelp,
.media = &media_xem,
- GEN12_DISPLAY,
- .display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
PLATFORM(XE_ALDERLAKE_P),
.has_llc = 1,
.require_force_probe = true,
@@ -290,9 +215,6 @@ static const struct xe_device_desc adl_p_desc = {
static const struct xe_device_desc adl_n_desc = {
.graphics = &graphics_xelp,
.media = &media_xem,
- GEN12_DISPLAY,
- .display.has_hti = 1,
- .display.has_psr_hw_tracking = 0,
PLATFORM(XE_ALDERLAKE_N),
.has_llc = 1,
.require_force_probe = true,
@@ -304,7 +226,6 @@ static const struct xe_device_desc adl_n_desc = {
static const struct xe_device_desc dg1_desc = {
.graphics = &graphics_xelpp,
.media = &media_xem,
- GEN12_DISPLAY,
DGFX_FEATURES,
PLATFORM(XE_DG1),
.require_force_probe = true,
@@ -339,9 +260,6 @@ static const struct xe_device_desc dg2_desc = {
.require_force_probe = true,
DG2_FEATURES,
- GEN13_DISPLAY,
- .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
};
static const struct xe_device_desc pvc_desc = {
@@ -355,13 +273,10 @@ static const struct xe_device_desc mtl_desc = {
/* .graphics and .media determined via GMD_ID */
.require_force_probe = true,
PLATFORM(XE_METEORLAKE),
- GEN13_DISPLAY,
- .display.ver = 14,
- .display.has_cdclk_crawl = 1,
- .display.has_cdclk_squash = 1,
};
#undef PLATFORM
+__diag_pop();
/* Map of GMD_ID values to graphics IP */
static struct gmdid_map graphics_ip_map[] = {
@@ -606,7 +521,6 @@ static int xe_info_init(struct xe_device *xe,
xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
xe->info.has_range_tlb_invalidation = graphics_desc->has_range_tlb_invalidation;
xe->info.has_link_copy_engine = graphics_desc->has_link_copy_engine;
- xe->info.display = desc->display;
/*
* All platforms have at least one primary GT. Any platform with media
@@ -716,6 +630,8 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (err)
goto err_drm_put;
+ xe_display_info_init(xe);
+
drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) dma_m_s:%d tc:%d",
desc->platform_name,
subplatform_desc ? subplatform_desc->name : "",
--
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