From 0d93b64e21ede7949f51ca360d69ba450164e552 Mon Sep 17 00:00:00 2001
From: Matthew Auld <matthew.auld@intel.com>
Date: Mon, 18 Dec 2023 11:45:49 +0000
Subject: [PATCH] drm/xe/vm: support incoherent access for userptr
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/xe/xe_bo.c | 5 -----
drivers/gpu/drm/xe/xe_device.c | 5 +++++
drivers/gpu/drm/xe/xe_device.h | 2 ++
drivers/gpu/drm/xe/xe_vm.c | 13 +++++++++++--
4 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 82055b070e8a0..dc869f2901833 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -285,11 +285,6 @@ struct xe_ttm_tt {
bool cache_dirty;
};
-static bool xe_device_can_bypass_cpu_caches(struct xe_device *xe)
-{
- return !IS_DGFX(xe) && !xe->info.has_llc;
-}
-
/*
* xe_bo_initial_clflush() - clflush system memory pages, if needed.
* @bo: The object to clflush. The object must be locked and be allocated in
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index d9ae77fe7382d..fe463ce5e4719 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -616,6 +616,11 @@ u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size)
DIV_ROUND_UP(size, NUM_BYTES_PER_CCS_BYTE(xe)) : 0;
}
+bool xe_device_can_bypass_cpu_caches(struct xe_device *xe)
+{
+ return !IS_DGFX(xe) && !xe->info.has_llc;
+}
+
bool xe_device_mem_access_ongoing(struct xe_device *xe)
{
if (xe_pm_read_callback_task(xe) != NULL)
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 3da83b2332063..997bd7886415c 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -170,4 +170,6 @@ static inline bool xe_device_has_sriov(struct xe_device *xe)
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
+bool xe_device_can_bypass_cpu_caches(struct xe_device *xe);
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 2b193dc1d544d..68813538198c1 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -8,6 +8,7 @@
#include <linux/dma-fence-array.h>
#include <linux/nospec.h>
+#include <drm/drm_cache.h>
#include <drm/drm_exec.h>
#include <drm/drm_print.h>
#include <drm/ttm/ttm_execbuf_util.h>
@@ -152,6 +153,16 @@ int xe_vma_userptr_pin_pages(struct xe_vma *vma)
goto out;
}
+#if defined(CONFIG_X86)
+ if (xe_device_can_bypass_cpu_caches(xe) &&
+ xe_pat_index_get_coh_mode(xe, vma->pat_index)) {
+ drm_clflush_sg(vma->userptr.sg);
+ xe_assert(xe, !IS_DGFX(xe));
+ }
+#else
+ xe_assert(xe, !xe_device_can_bypass_cpu_caches(xe));
+#endif
+
for (i = 0; i < pinned; ++i) {
if (!read_only) {
lock_page(pages[i]);
@@ -2775,8 +2786,6 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe,
op == DRM_XE_VM_BIND_OP_UNMAP_ALL) ||
XE_IOCTL_DBG(xe, obj &&
op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
- XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
- op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
XE_IOCTL_DBG(xe, obj &&
op == DRM_XE_VM_BIND_OP_PREFETCH) ||
XE_IOCTL_DBG(xe, prefetch_region &&
--
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