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Sergii Romantsov authored
Intel ppgtt-model requires memory addresses to be aligned by page size. Test explores cases with cached memory-buckets and sizes above cached. v2: copyright updated v3: logic moved to piglit_init, code fixes (I.Romanick) CC: Kenneth Graunke <kenneth@whitecape.org> CC: Lionel G Landwerlin <lionel.g.landwerlin@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997 Tests: 24839663a402 (intel/ppgtt: memory address alignment) Tests: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.) Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Tested-by: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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