freedreno/a6xx: enable UBWC for depth/stencil
First few patches are mostly unrelated, I just haven't had a chance to run them thru deqp on their own.
The basic issue is that for certain z/s blits, we currently re-write the blit into an equivalently sized RGBA format and fix up the blit mask. This falls apart when UBWC is enabled for z/s, because UBWC interprets the data differently for z24s8 vs r8g8b8a8. Fortunately the hardware provides a format which is basically z24s8_as_r8g8b8a8. Everything works similarly to re-interpreting the z24s8/z24x8 as r8g8b8a8, except UBWC meta data is handled appropriately.
After trying a few different approaches to handle this, the most straightforward solution is to add a new equivalent
PIPE_FORMAT_Z24_UNORM_S8_UINT_AS_R8G8B8A8 that maps to this special hw format, and then do things more or less the same as before. This avoid introducing a new pipe-cap and changes to
Dropping the WIP flag for now, since there are no more remaining deqp regressions to debug.