radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables

It varies depending on si_shader_key::as_ngg.

src/gallium/drivers/radeonsi/gfx10_shader_ngg.c

@@ -504,7 +504,7 @@ static unsigned ngg_nogs_vertex_size(struct si_shader *shader)
 	 * used for padding to reduce LDS bank conflicts. */
 	if (shader->selector->so.num_outputs)
 		lds_vertex_size = 4 * shader->selector->info.num_outputs + 1;
-	if (shader->selector->ngg_writes_edgeflag)
+	if (shader->selector->info.writes_edgeflag)
 		lds_vertex_size = MAX2(lds_vertex_size, 1);
 
 	return lds_vertex_size;
@@ -544,7 +544,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
 
 	LLVMValueRef vertex_ptr = NULL;
 
-	if (sel->so.num_outputs || sel->ngg_writes_edgeflag)
+	if (sel->so.num_outputs || sel->info.writes_edgeflag)
 		vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
 
 	for (unsigned i = 0; i < info->num_outputs; i++) {
@@ -569,7 +569,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
 
 		/* Store the edgeflag at the end (if streamout is enabled) */
 		if (info->output_semantic_name[i] == TGSI_SEMANTIC_EDGEFLAG &&
-		    sel->ngg_writes_edgeflag) {
+		    sel->info.writes_edgeflag) {
 			LLVMValueRef edgeflag = LLVMBuildLoad(builder, addrs[4 * i], "");
 			/* The output is a float, but the hw expects a 1-bit integer. */
 			edgeflag = LLVMBuildFPToUI(ctx->ac.builder, edgeflag, ctx->i32, "");
@@ -641,7 +641,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
 
 	LLVMValueRef user_edgeflags[3] = {};
 
-	if (sel->ngg_writes_edgeflag) {
+	if (sel->info.writes_edgeflag) {
 		/* Streamout already inserted the barrier, so don't insert it again. */
 		if (!sel->so.num_outputs)
 			ac_build_s_barrier(&ctx->ac);
@@ -667,7 +667,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
 	if (ctx->type == PIPE_SHADER_VERTEX &&
 	    ctx->shader->key.mono.u.vs_export_prim_id) {
 		/* Streamout and edge flags use LDS. Make it idle, so that we can reuse it. */
-		if (sel->so.num_outputs || sel->ngg_writes_edgeflag)
+		if (sel->so.num_outputs || sel->info.writes_edgeflag)
 			ac_build_s_barrier(&ctx->ac);
 
 		ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
@@ -756,7 +756,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
 					    LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
 			prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
 
-			if (sel->ngg_writes_edgeflag) {
+			if (sel->info.writes_edgeflag) {
 				tmp2 = LLVMBuildLoad(builder, user_edgeflags[i], "");
 				prim.edgeflag[i] = LLVMBuildAnd(builder, prim.edgeflag[i],
 								tmp2, "");

src/gallium/drivers/radeonsi/si_shader.c

@@ -2988,13 +2988,16 @@ void si_llvm_export_vs(struct si_shader_context *ctx,
 		pos_args[0].out[3] = ctx->ac.f32_1;  /* W */
 	}
 
+	bool pos_writes_edgeflag = shader->selector->info.writes_edgeflag &&
+				   !shader->key.as_ngg;
+
 	/* Write the misc vector (point size, edgeflag, layer, viewport). */
 	if (shader->selector->info.writes_psize ||
-	    shader->selector->pos_writes_edgeflag ||
+	    pos_writes_edgeflag ||
 	    shader->selector->info.writes_viewport_index ||
 	    shader->selector->info.writes_layer) {
 		pos_args[1].enabled_channels = shader->selector->info.writes_psize |
-					       (shader->selector->pos_writes_edgeflag << 1) |
+					       (pos_writes_edgeflag << 1) |
 					       (shader->selector->info.writes_layer << 2);
 
 		pos_args[1].valid_mask = 0; /* EXEC mask */
@@ -3009,7 +3012,7 @@ void si_llvm_export_vs(struct si_shader_context *ctx,
 		if (shader->selector->info.writes_psize)
 			pos_args[1].out[0] = psize_value;
 
-		if (shader->selector->pos_writes_edgeflag) {
+		if (pos_writes_edgeflag) {
 			/* The output is a float, but the hw expects an integer
 			 * with the first bit containing the edge flag. */
 			edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,

src/gallium/drivers/radeonsi/si_shader.h

@@ -336,8 +336,6 @@ struct si_shader_selector {
 	bool		vs_needs_prolog;
 	bool		force_correct_derivs_after_kill;
 	bool		prim_discard_cs_allowed;
-	bool		ngg_writes_edgeflag;
-	bool		pos_writes_edgeflag;
 	unsigned	pa_cl_vs_out_cntl;
 	ubyte		clipdist_mask;
 	ubyte		culldist_mask;

src/gallium/drivers/radeonsi/si_state_shaders.c

@@ -2726,14 +2726,6 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
 		!sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
 		!sel->so.num_outputs;
 
-	if (sel->type == PIPE_SHADER_VERTEX &&
-	    sel->info.writes_edgeflag) {
-		if (sscreen->info.chip_class >= GFX10)
-			sel->ngg_writes_edgeflag = true;
-		else
-			sel->pos_writes_edgeflag = true;
-	}
-
 	switch (sel->type) {
 	case PIPE_SHADER_GEOMETRY:
 		sel->gs_output_prim =
@@ -2865,11 +2857,11 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
 
 	/* PA_CL_VS_OUT_CNTL */
 	bool misc_vec_ena =
-		sel->info.writes_psize || sel->pos_writes_edgeflag ||
+		sel->info.writes_psize || sel->info.writes_edgeflag ||
 		sel->info.writes_layer || sel->info.writes_viewport_index;
 	sel->pa_cl_vs_out_cntl =
 		S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
-		S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
+		S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
 		S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
 		S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
 		S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |