Commit a6b64d6d authored by Dave Airlie's avatar Dave Airlie

virgl: add ARB_texture_view support

Reviewed-By: Gert Wollny's avatarGert Wollny <gert.wollny@collabora.com>
parent ff6db94c
......@@ -187,7 +187,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
GL_ARB_texture_buffer_range DONE (freedreno, nv50, i965, llvmpipe, virgl)
GL_ARB_texture_query_levels DONE (all drivers that support GLSL 1.30)
GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample)
GL_ARB_texture_view DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr)
GL_ARB_texture_view DONE (freedreno, i965, nv50, llvmpipe, softpipe, swr, virgl)
GL_ARB_vertex_attrib_binding DONE (all drivers)
......
......@@ -589,12 +589,15 @@ int virgl_encode_sampler_view(struct virgl_context *ctx,
const struct pipe_sampler_view *state)
{
unsigned elem_size = util_format_get_blocksize(state->format);
struct virgl_screen *rs = virgl_screen(ctx->base.screen);
uint32_t tmp;
uint32_t dword_fmt_target = state->format;
virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW, VIRGL_OBJ_SAMPLER_VIEW_SIZE));
virgl_encoder_write_dword(ctx->cbuf, handle);
virgl_encoder_write_res(ctx, res);
virgl_encoder_write_dword(ctx->cbuf, state->format);
if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW)
dword_fmt_target |= (state->target << 24);
virgl_encoder_write_dword(ctx->cbuf, dword_fmt_target);
if (res->u.b.target == PIPE_BUFFER) {
virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
......
......@@ -200,6 +200,7 @@ enum virgl_formats {
/* These are used by the capability_bits field in virgl_caps_v2. */
#define VIRGL_CAP_NONE 0
#define VIRGL_CAP_TGSI_INVARIANT (1 << 0)
#define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
#define VIRGL_BIND_RENDER_TARGET (1 << 1)
......
......@@ -217,6 +217,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
return vscreen->caps.caps.v1.bset.has_fp64;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return vscreen->caps.caps.v2.max_shader_patch_varyings;
case PIPE_CAP_SAMPLER_VIEW_TARGET:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
......@@ -225,7 +227,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_CLIP_HALFZ:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
......
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