Commit a5df0fa0 authored by José Casanova Crespo's avatar José Casanova Crespo

v3d: writes to magic registers aren't RF writes after THREND

Shaders must not attempt to write to the register files in the last
three instructions, but that doesn't include the magic registers:

nop                  ; nop               ; thrsw; ldtmu.- *** ERROR ***
nop                  ; nop
nop                  ; nop

v2: Simplify validation rules. (Eric Anholt)
v3: Adjust validation even more. (Eric Anholt)
Reviewed-by: Eric Anholt's avatarEric Anholt <eric@anholt.net>
parent 1dce75c1
Pipeline #61518 passed with stages
in 18 minutes and 41 seconds
......@@ -258,8 +258,10 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst)
fail_instr(state, "RF write after THREND");
}
if (v3d_qpu_sig_writes_address(devinfo, &inst->sig))
if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) &&
!inst->sig_magic) {
fail_instr(state, "RF write after THREND");
}
/* GFXH-1625: No TMUWT in the last instruction */
if (state->last_thrsw_ip - state->ip == 2 &&
......
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