Commit 3fbdcd94 authored by Samuel Pitoiset's avatar Samuel Pitoiset

amd: remove support for LLVM 6.0

User are encouraged to switch to LLVM 7.0 released in September 2018.
Signed-off-by: Samuel Pitoiset's avatarSamuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
parent 3b2ad8b2
......@@ -107,8 +107,8 @@ dnl LLVM versions
LLVM_REQUIRED_GALLIUM=3.3.0
LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=6.0.0
LLVM_REQUIRED_RADV=6.0.0
LLVM_REQUIRED_RADEONSI=7.0.0
LLVM_REQUIRED_RADV=7.0.0
LLVM_REQUIRED_SWR=6.0.0
dnl Check for progs
......
......@@ -1176,7 +1176,7 @@ if with_gallium_opencl
endif
if with_amd_vk or with_gallium_radeonsi
_llvm_version = '>= 6.0.0'
_llvm_version = '>= 7.0.0'
elif with_gallium_swr
_llvm_version = '>= 6.0.0'
elif with_gallium_opencl or with_gallium_r600
......
......@@ -75,7 +75,7 @@ ac_llvm_context_init(struct ac_llvm_context *ctx,
ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
ctx->intptr = HAVE_32BIT_POINTERS ? ctx->i32 : ctx->i64;
ctx->intptr = ctx->i32;
ctx->f16 = LLVMHalfTypeInContext(ctx->context);
ctx->f32 = LLVMFloatTypeInContext(ctx->context);
ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
......@@ -1403,12 +1403,10 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
int idx,
LLVMValueRef val)
{
unsigned tl_lanes[4], trbl_lanes[4];
LLVMValueRef tl, trbl, args[2];
LLVMValueRef result;
if (HAVE_LLVM >= 0x0700) {
unsigned tl_lanes[4], trbl_lanes[4];
for (unsigned i = 0; i < 4; ++i) {
tl_lanes[i] = i & mask;
trbl_lanes[i] = (i & mask) + idx;
......@@ -1420,82 +1418,13 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
trbl = ac_build_quad_swizzle(ctx, val,
trbl_lanes[0], trbl_lanes[1],
trbl_lanes[2], trbl_lanes[3]);
} else if (ctx->chip_class >= VI) {
LLVMValueRef thread_id, tl_tid, trbl_tid;
thread_id = ac_get_thread_id(ctx);
tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
LLVMConstInt(ctx->i32, mask, false), "");
trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
LLVMConstInt(ctx->i32, idx, false), "");
args[0] = LLVMBuildMul(ctx->builder, tl_tid,
LLVMConstInt(ctx->i32, 4, false), "");
args[1] = val;
tl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.bpermute", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
LLVMConstInt(ctx->i32, 4, false), "");
trbl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.bpermute", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
} else {
uint32_t masks[2] = {};
switch (mask) {
case AC_TID_MASK_TOP_LEFT:
masks[0] = 0x8000;
if (idx == 1)
masks[1] = 0x8055;
else
masks[1] = 0x80aa;
break;
case AC_TID_MASK_TOP:
masks[0] = 0x8044;
masks[1] = 0x80ee;
break;
case AC_TID_MASK_LEFT:
masks[0] = 0x80a0;
masks[1] = 0x80f5;
break;
default:
assert(0);
}
args[0] = val;
args[1] = LLVMConstInt(ctx->i32, masks[0], false);
tl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.swizzle", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
args[1] = LLVMConstInt(ctx->i32, masks[1], false);
trbl = ac_build_intrinsic(ctx,
"llvm.amdgcn.ds.swizzle", ctx->i32,
args, 2,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_CONVERGENT);
}
tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
if (HAVE_LLVM >= 0x0700) {
result = ac_build_intrinsic(ctx,
"llvm.amdgcn.wqm.f32", ctx->f32,
result = ac_build_intrinsic(ctx, "llvm.amdgcn.wqm.f32", ctx->f32,
&result, 1, 0);
}
return result;
}
......@@ -1740,171 +1669,6 @@ static const char *get_atomic_name(enum ac_atomic_op op)
unreachable("bad atomic op");
}
/* LLVM 6 and older */
static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
struct ac_image_args *a)
{
LLVMValueRef args[16];
LLVMTypeRef retty = ctx->v4f32;
const char *name = NULL;
const char *atomic_subop = "";
char intr_name[128], coords_type[64];
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
bool atomic = a->opcode == ac_image_atomic ||
a->opcode == ac_image_atomic_cmpswap;
bool da = a->dim == ac_image_cube ||
a->dim == ac_image_1darray ||
a->dim == ac_image_2darray ||
a->dim == ac_image_2darraymsaa;
if (a->opcode == ac_image_get_lod)
da = false;
unsigned num_coords =
a->opcode != ac_image_get_resinfo ? ac_num_coords(a->dim) : 0;
LLVMValueRef addr;
unsigned num_addr = 0;
if (a->opcode == ac_image_get_lod) {
switch (a->dim) {
case ac_image_1darray:
num_coords = 1;
break;
case ac_image_2darray:
case ac_image_cube:
num_coords = 2;
break;
default:
break;
}
}
if (a->offset)
args[num_addr++] = ac_to_integer(ctx, a->offset);
if (a->bias)
args[num_addr++] = ac_to_integer(ctx, a->bias);
if (a->compare)
args[num_addr++] = ac_to_integer(ctx, a->compare);
if (a->derivs[0]) {
unsigned num_derivs = ac_num_derivs(a->dim);
for (unsigned i = 0; i < num_derivs; ++i)
args[num_addr++] = ac_to_integer(ctx, a->derivs[i]);
}
for (unsigned i = 0; i < num_coords; ++i)
args[num_addr++] = ac_to_integer(ctx, a->coords[i]);
if (a->lod)
args[num_addr++] = ac_to_integer(ctx, a->lod);
unsigned pad_goal = util_next_power_of_two(num_addr);
while (num_addr < pad_goal)
args[num_addr++] = LLVMGetUndef(ctx->i32);
addr = ac_build_gather_values(ctx, args, num_addr);
unsigned num_args = 0;
if (atomic || a->opcode == ac_image_store || a->opcode == ac_image_store_mip) {
args[num_args++] = a->data[0];
if (a->opcode == ac_image_atomic_cmpswap)
args[num_args++] = a->data[1];
}
unsigned coords_arg = num_args;
if (sample)
args[num_args++] = ac_to_float(ctx, addr);
else
args[num_args++] = ac_to_integer(ctx, addr);
args[num_args++] = a->resource;
if (sample)
args[num_args++] = a->sampler;
if (!atomic) {
args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
if (sample)
args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
args[num_args++] = a->cache_policy & ac_glc ? ctx->i1true : ctx->i1false;
args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
args[num_args++] = ctx->i1false; /* lwe */
args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
} else {
args[num_args++] = ctx->i1false; /* r128 */
args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
}
switch (a->opcode) {
case ac_image_sample:
name = "llvm.amdgcn.image.sample";
break;
case ac_image_gather4:
name = "llvm.amdgcn.image.gather4";
break;
case ac_image_load:
name = "llvm.amdgcn.image.load";
break;
case ac_image_load_mip:
name = "llvm.amdgcn.image.load.mip";
break;
case ac_image_store:
name = "llvm.amdgcn.image.store";
retty = ctx->voidt;
break;
case ac_image_store_mip:
name = "llvm.amdgcn.image.store.mip";
retty = ctx->voidt;
break;
case ac_image_atomic:
case ac_image_atomic_cmpswap:
name = "llvm.amdgcn.image.atomic.";
retty = ctx->i32;
if (a->opcode == ac_image_atomic_cmpswap) {
atomic_subop = "cmpswap";
} else {
atomic_subop = get_atomic_name(a->atomic);
}
break;
case ac_image_get_lod:
name = "llvm.amdgcn.image.getlod";
break;
case ac_image_get_resinfo:
name = "llvm.amdgcn.image.getresinfo";
break;
default:
unreachable("invalid image opcode");
}
ac_build_type_name_for_intr(LLVMTypeOf(args[coords_arg]), coords_type,
sizeof(coords_type));
if (atomic) {
snprintf(intr_name, sizeof(intr_name), "llvm.amdgcn.image.atomic.%s.%s",
atomic_subop, coords_type);
} else {
bool lod_suffix =
a->lod && (a->opcode == ac_image_sample || a->opcode == ac_image_gather4);
snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.v4f32.%s.v8i32",
name,
a->compare ? ".c" : "",
a->bias ? ".b" :
lod_suffix ? ".l" :
a->derivs[0] ? ".d" :
a->level_zero ? ".lz" : "",
a->offset ? ".o" : "",
coords_type);
}
LLVMValueRef result =
ac_build_intrinsic(ctx, intr_name, retty, args, num_args,
a->attributes);
if (!sample && retty == ctx->v4f32) {
result = LLVMBuildBitCast(ctx->builder, result,
ctx->v4i32, "");
}
return result;
}
LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
struct ac_image_args *a)
{
......@@ -1929,9 +1693,6 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
(a->level_zero ? 1 : 0) +
(a->derivs[0] ? 1 : 0) <= 1);
if (HAVE_LLVM < 0x0700)
return ac_build_image_opcode_llvm6(ctx, a);
if (a->opcode == ac_image_get_lod) {
switch (dim) {
case ac_image_1darray:
......@@ -2720,9 +2481,6 @@ LLVMTypeRef ac_array_in_const_addr_space(LLVMTypeRef elem_type)
LLVMTypeRef ac_array_in_const32_addr_space(LLVMTypeRef elem_type)
{
if (!HAVE_32BIT_POINTERS)
return ac_array_in_const_addr_space(elem_type);
return LLVMPointerType(LLVMArrayType(elem_type, 0),
AC_ADDR_SPACE_CONST_32BIT);
}
......
......@@ -34,14 +34,12 @@
extern "C" {
#endif
#define HAVE_32BIT_POINTERS (HAVE_LLVM >= 0x0700)
enum {
AC_ADDR_SPACE_FLAT = HAVE_LLVM >= 0x0700 ? 0 : 4, /* Slower than global. */
AC_ADDR_SPACE_FLAT = 0, /* Slower than global. */
AC_ADDR_SPACE_GLOBAL = 1,
AC_ADDR_SPACE_GDS = HAVE_LLVM >= 0x0700 ? 2 : 5,
AC_ADDR_SPACE_GDS = 2,
AC_ADDR_SPACE_LDS = 3,
AC_ADDR_SPACE_CONST = HAVE_LLVM >= 0x0700 ? 4 : 2, /* Global allowing SMEM. */
AC_ADDR_SPACE_CONST = 4, /* Global allowing SMEM. */
AC_ADDR_SPACE_CONST_32BIT = 6, /* same as CONST, but the pointer type has 32 bits */
};
......
......@@ -39,9 +39,6 @@
#include <llvm/Transforms/IPO.h>
#include <llvm/IR/LegacyPassManager.h>
#if HAVE_LLVM < 0x0700
#include "llvm/Support/raw_ostream.h"
#endif
void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes)
{
......@@ -132,9 +129,7 @@ struct ac_compiler_passes *ac_create_llvm_passes(LLVMTargetMachineRef tm)
llvm::TargetMachine *TM = reinterpret_cast<llvm::TargetMachine*>(tm);
if (TM->addPassesToEmitFile(p->passmgr, p->ostream,
#if HAVE_LLVM >= 0x0700
nullptr,
#endif
llvm::TargetMachine::CGFT_ObjectFile)) {
fprintf(stderr, "amd: TargetMachine can't emit a file of this type!\n");
delete p;
......@@ -170,7 +165,5 @@ void ac_llvm_add_barrier_noop_pass(LLVMPassManagerRef passmgr)
void ac_enable_global_isel(LLVMTargetMachineRef tm)
{
#if HAVE_LLVM >= 0x0700
reinterpret_cast<llvm::TargetMachine*>(tm)->setGlobalISel(true);
#endif
}
......@@ -30,9 +30,7 @@
#include <llvm-c/Support.h>
#include <llvm-c/Transforms/IPO.h>
#include <llvm-c/Transforms/Scalar.h>
#if HAVE_LLVM >= 0x0700
#include <llvm-c/Transforms/Utils.h>
#endif
#include "c11/threads.h"
#include "gallivm/lp_bld_misc.h"
#include "util/u_math.h"
......@@ -132,9 +130,9 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_RAVEN:
return "gfx902";
case CHIP_VEGA12:
return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
return "gfx904";
case CHIP_VEGA20:
return HAVE_LLVM >= 0x0700 ? "gfx906" : "gfx902";
return "gfx906";
case CHIP_RAVEN2:
return "gfx902"; /* TODO: use gfx909 when it's available */
default:
......@@ -303,7 +301,6 @@ ac_count_scratch_private_memory(LLVMValueRef function)
bool
ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
bool okay_to_leak_target_library_info,
enum radeon_family family,
enum ac_target_machine_options tm_options)
{
......@@ -324,12 +321,10 @@ ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
goto fail;
}
if (okay_to_leak_target_library_info || (HAVE_LLVM >= 0x0700)) {
compiler->target_library_info =
ac_create_target_library_info(triple);
if (!compiler->target_library_info)
goto fail;
}
compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
tm_options & AC_TM_CHECK_IR);
......@@ -347,11 +342,8 @@ ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
{
if (compiler->passmgr)
LLVMDisposePassManager(compiler->passmgr);
#if HAVE_LLVM >= 0x0700
/* This crashes on LLVM 5.0 and 6.0 and Ubuntu 18.04, so leak it there. */
if (compiler->target_library_info)
ac_dispose_target_library_info(compiler->target_library_info);
#endif
if (compiler->low_opt_tm)
LLVMDisposeTargetMachine(compiler->low_opt_tm);
if (compiler->tm)
......
......@@ -134,7 +134,6 @@ void ac_init_llvm_once(void);
bool ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
bool okay_to_leak_target_library_info,
enum radeon_family family,
enum ac_target_machine_options tm_options);
void ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler);
......
......@@ -429,12 +429,7 @@ static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
{
LLVMValueRef result;
if (HAVE_LLVM < 0x0700) {
LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
} else {
/* FIXME: LLVM 7 returns incorrect result when count is 0.
/* FIXME: LLVM 7+ returns incorrect result when count is 0.
* https://bugs.freedesktop.org/show_bug.cgi?id=107276
*/
LLVMValueRef zero = ctx->i32_0;
......@@ -444,7 +439,6 @@ static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
result = LLVMBuildSelect(ctx->builder, icond1, srcs[0], result, "");
result = LLVMBuildSelect(ctx->builder, icond2, zero, result, "");
}
return result;
}
......
......@@ -594,7 +594,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
if (loc->sgpr_idx == -1)
return;
assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
assert(loc->num_sgprs == 1);
assert(!loc->indirect);
radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
......@@ -624,14 +624,12 @@ radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
struct radv_userdata_info *loc = &locs->descriptor_sets[start];
unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
radv_emit_shader_pointer_head(cs, sh_offset, count,
HAVE_32BIT_POINTERS);
radv_emit_shader_pointer_head(cs, sh_offset, count, true);
for (int i = 0; i < count; i++) {
struct radv_descriptor_set *set =
descriptors_state->sets[start + i];
radv_emit_shader_pointer_body(device, cs, set->va,
HAVE_32BIT_POINTERS);
radv_emit_shader_pointer_body(device, cs, set->va, true);
}
}
}
......@@ -1740,8 +1738,7 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_descriptor_state *descriptors_state =
radv_get_descriptors_state(cmd_buffer, bind_point);
uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
uint32_t size = MAX_SETS * 4 * ptr_size;
uint32_t size = MAX_SETS * 4;
uint32_t offset;
void *ptr;
......@@ -1750,14 +1747,12 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
return;
for (unsigned i = 0; i < MAX_SETS; i++) {
uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
uint32_t *uptr = ((uint32_t *)ptr) + i;
uint64_t set_va = 0;
struct radv_descriptor_set *set = descriptors_state->sets[i];
if (descriptors_state->valid & (1u << i))
set_va = set->va;
uptr[0] = set_va & 0xffffffff;
if (ptr_size == 2)
uptr[1] = set_va >> 32;
}
uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
......
......@@ -747,7 +747,7 @@ void radv_GetPhysicalDeviceFeatures(
.shaderCullDistance = true,
.shaderFloat64 = true,
.shaderInt64 = true,
.shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && HAVE_LLVM >= 0x700,
.shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
.sparseBinding = true,
.variableMultisampleRate = true,
.inheritedQueries = true,
......@@ -789,7 +789,7 @@ void radv_GetPhysicalDeviceFeatures2(
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
VkPhysicalDevice16BitStorageFeatures *features =
(VkPhysicalDevice16BitStorageFeatures*)ext;
bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
bool enabled = pdevice->rad_info.chip_class >= VI;
features->storageBuffer16BitAccess = enabled;
features->uniformAndStorageBuffer16BitAccess = enabled;
features->storagePushConstant16 = enabled;
......
......@@ -51,7 +51,7 @@ class Extension:
# and dEQP-VK.api.info.device fail due to the duplicated strings.
EXTENSIONS = [
Extension('VK_ANDROID_native_buffer', 5, 'ANDROID && device->rad_info.has_syncobj_wait_for_submit'),
Extension('VK_KHR_16bit_storage', 1, 'HAVE_LLVM >= 0x0700'),
Extension('VK_KHR_16bit_storage', 1, True),
Extension('VK_KHR_bind_memory2', 1, True),
Extension('VK_KHR_create_renderpass2', 1, True),
Extension('VK_KHR_dedicated_allocation', 1, True),
......
......@@ -40,7 +40,6 @@ public:
bool init(void)
{
if (!ac_init_llvm_compiler(&llvm_info,
true,
family,
tm_options))
return false;
......@@ -99,7 +98,6 @@ bool radv_compile_to_binary(struct ac_llvm_compiler *info,
}
bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
bool okay_to_leak_target_library_info,
bool thread_compiler,
enum radeon_family family,
enum ac_target_machine_options tm_options)
......@@ -125,7 +123,6 @@ bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
}
if (!ac_init_llvm_compiler(info,
okay_to_leak_target_library_info,
family,
tm_options))
return false;
......
......@@ -33,9 +33,7 @@
#include <llvm-c/Core.h>
#include <llvm-c/TargetMachine.h>
#include <llvm-c/Transforms/Scalar.h>
#if HAVE_LLVM >= 0x0700
#include <llvm-c/Transforms/Utils.h>
#endif
#include "sid.h"
#include "gfx9d.h"
......@@ -568,8 +566,7 @@ set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
static void
set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
{
bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
idx != AC_UD_SCRATCH_RING_OFFSETS;
bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
}
......@@ -583,7 +580,7 @@ set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
assert(ud_info);
set_loc(ud_info, sgpr_idx, HAVE_32BIT_POINTERS ? 1 : 2, indirect);
set_loc(ud_info, sgpr_idx, 1, indirect);
if (!indirect)
locs->descriptor_sets_enabled |= 1 << idx;
......@@ -624,7 +621,7 @@ count_vs_user_sgprs(struct radv_shader_context *ctx)
uint8_t count = 0;
if (ctx->shader_info->info.vs.has_vertex_buffers)
count += HAVE_32BIT_POINTERS ? 1 : 2;
count++;
count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
return count;
......@@ -693,14 +690,14 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
user_sgpr_count++;
if (ctx->shader_info->info.loads_push_constants)
user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
user_sgpr_count++;
uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
uint32_t num_desc_set =
util_bitcount(ctx->shader_info->info.desc_set_used_mask);
if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
if (remaining_sgprs < num_desc_set) {
user_sgpr_info->indirect_all_descriptor_sets = true;
}
}
......
......@@ -1243,7 +1243,7 @@ radv_emit_shader_pointer(struct radv_device *device,
struct radeon_cmdbuf *cs,
uint32_t sh_offset, uint64_t va, bool global)
{
bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
bool use_32bit_pointers = !global;
radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
......
......@@ -600,7 +600,7 @@ shader_variant_create(struct radv_device *device,
thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
radv_init_llvm_once();
radv_init_llvm_compiler(&ac_llvm, false,
radv_init_llvm_compiler(&ac_llvm,
thread_compiler,
chip_family, tm_options);
if (gs_copy_shader) {
......
......@@ -27,7 +27,6 @@ extern "C" {
#endif
bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
bool okay_to_leak_target_library_info,
bool thread_compiler,
enum radeon_family family,
enum ac_target_machine_options tm_options);
......
......@@ -2055,7 +2055,7 @@ static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
unsigned sh_offset,
unsigned pointer_count)
{
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (HAVE_32BIT_POINTERS ? 1 : 2), 0));
radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0));
radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
}
......@@ -2065,10 +2065,7 @@ static void si_emit_shader_pointer_body(struct si_screen *sscreen,
{
radeon_emit(cs, va);
if (HAVE_32BIT_POINTERS)
assert(va == 0 || (va >> 32) == sscreen->info.address32_hi);
else
radeon_emit(cs, va >> 32);
}
static void si_emit_shader_pointer(struct si_context *sctx,
......@@ -2106,25 +2103,6 @@ static void si_emit_consecutive_shader_pointers(struct si_context *sctx,
}
}
static void si_emit_disjoint_shader_pointers(struct si_context *sctx,
unsigned pointer_mask,
unsigned sh_base)
{
if (!sh_base)
return;
struct radeon_cmdbuf *cs = sctx->gfx_cs;
unsigned mask = sctx->shader_pointers_dirty & pointer_mask;
while (mask) {
struct si_descriptors *descs = &sctx->descriptors[u_bit_scan(&mask)];
unsigned sh_offset = sh_base + descs->shader_userdata_offset;
si_emit_shader_pointer_head(cs, sh_offset, 1);
si_emit_shader_pointer_body(sctx->screen, cs, descs->gpu_address);
}
}
static void si_emit_global_shader_pointers(struct si_context *sctx,
struct si_descriptors *descs)
{
......@@ -2164,17 +2142,10 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx)
sh_base[PIPE_SHADER_TESS_EVAL]);
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT),
sh_base[PIPE_SHADER_FRAGMENT]);
if (HAVE_32BIT_POINTERS || sctx->chip_class <= VI) {
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
sh_base[PIPE_SHADER_TESS_CTRL]);
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
sh_base[PIPE_SHADER_GEOMETRY]);
} else {
si_emit_disjoint_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL),
sh_base[PIPE_SHADER_TESS_CTRL]);
si_emit_disjoint_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
sh_base[PIPE_SHADER_GEOMETRY]);
}
sctx->shader_pointers_dirty &=
~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
......@@ -2665,10 +2636,6 @@ void si_init_all_descriptors(struct si_context *sctx)
{
int i;
#if !HAVE_32BIT_POINTERS
STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES % 2 == 0);
#endif
for (i = 0; i < SI_NUM_SHADERS; i++) {
bool is_2nd = sctx->chip_class >= GFX9 &&
(i == PIPE_SHADER_TESS_CTRL ||
......@@ -2699,7 +2666,6 @@ void si_init_all_descriptors(struct si_context *sctx)
desc->slot_index_to_bind_directly = si_get_constbuf_slot(0);
if (is_2nd) {