iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.

This commit introduces a new Gallium driver for Intel Gen8+ GPUs,
named 'iris_dri.so' after the hardware.

Developed by:
- Kenneth Graunke (overall driver)
- Dave Airlie (shaders, conditional render, overflow query, Gen8 port)
- Chris Wilson (fencing, pinned memory, ...)
- Jordan Justen (compute shaders)
- Jason Ekstrand (image load store)
- Caio Marcelo de Oliveira Filho (tessellation control passthrough)
- Rafael Antognolli (auxiliary buffer fixes)
- The rest of the i965 contributors and the Mesa community
parent eac822ea
#ifndef IRIS
CHIPSET(0x29A2, i965, "Intel(R) 965G") CHIPSET(0x29A2, i965, "Intel(R) 965G")
CHIPSET(0x2992, i965, "Intel(R) 965Q") CHIPSET(0x2992, i965, "Intel(R) 965Q")
CHIPSET(0x2982, i965, "Intel(R) 965G") CHIPSET(0x2982, i965, "Intel(R) 965G")
...@@ -91,6 +92,11 @@ CHIPSET(0x0F32, byt, "Intel(R) Bay Trail") ...@@ -91,6 +92,11 @@ CHIPSET(0x0F32, byt, "Intel(R) Bay Trail")
CHIPSET(0x0F33, byt, "Intel(R) Bay Trail") CHIPSET(0x0F33, byt, "Intel(R) Bay Trail")
CHIPSET(0x0157, byt, "Intel(R) Bay Trail") CHIPSET(0x0157, byt, "Intel(R) Bay Trail")
CHIPSET(0x0155, byt, "Intel(R) Bay Trail") CHIPSET(0x0155, byt, "Intel(R) Bay Trail")
CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherrytrail)")
CHIPSET(0x22B1, chv, "Intel(R) HD Graphics XXX (Braswell)") /* Overridden in brw_get_renderer_string */
CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)")
CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)")
#endif
CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1") CHIPSET(0x1602, bdw_gt1, "Intel(R) Broadwell GT1")
CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1") CHIPSET(0x1606, bdw_gt1, "Intel(R) Broadwell GT1")
CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1") CHIPSET(0x160A, bdw_gt1, "Intel(R) Broadwell GT1")
...@@ -109,10 +115,6 @@ CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)") ...@@ -109,10 +115,6 @@ CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)")
CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)") CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)")
CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3") CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3")
CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3") CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3")
CHIPSET(0x22B0, chv, "Intel(R) HD Graphics (Cherrytrail)")
CHIPSET(0x22B1, chv, "Intel(R) HD Graphics XXX (Braswell)") /* Overridden in brw_get_renderer_string */
CHIPSET(0x22B2, chv, "Intel(R) HD Graphics (Cherryview)")
CHIPSET(0x22B3, chv, "Intel(R) HD Graphics (Cherryview)")
CHIPSET(0x1902, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)") CHIPSET(0x1902, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)")
CHIPSET(0x1906, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)") CHIPSET(0x1906, skl_gt1, "Intel(R) HD Graphics 510 (Skylake GT1)")
CHIPSET(0x190A, skl_gt1, "Intel(R) Skylake GT1") CHIPSET(0x190A, skl_gt1, "Intel(R) Skylake GT1")
......
...@@ -157,6 +157,7 @@ with_gallium_v3d = _drivers.contains('v3d') ...@@ -157,6 +157,7 @@ with_gallium_v3d = _drivers.contains('v3d')
with_gallium_panfrost = _drivers.contains('panfrost') with_gallium_panfrost = _drivers.contains('panfrost')
with_gallium_etnaviv = _drivers.contains('etnaviv') with_gallium_etnaviv = _drivers.contains('etnaviv')
with_gallium_tegra = _drivers.contains('tegra') with_gallium_tegra = _drivers.contains('tegra')
with_gallium_iris = _drivers.contains('iris')
with_gallium_i915 = _drivers.contains('i915') with_gallium_i915 = _drivers.contains('i915')
with_gallium_svga = _drivers.contains('svga') with_gallium_svga = _drivers.contains('svga')
with_gallium_virgl = _drivers.contains('virgl') with_gallium_virgl = _drivers.contains('virgl')
......
...@@ -60,7 +60,7 @@ option( ...@@ -60,7 +60,7 @@ option(
choices : [ choices : [
'', 'auto', 'kmsro', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno', '', 'auto', 'kmsro', 'radeonsi', 'r300', 'r600', 'nouveau', 'freedreno',
'swrast', 'v3d', 'vc4', 'etnaviv', 'tegra', 'i915', 'svga', 'virgl', 'swrast', 'v3d', 'vc4', 'etnaviv', 'tegra', 'i915', 'svga', 'virgl',
'swr', 'panfrost' 'swr', 'panfrost', 'iris'
], ],
description : 'List of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built' description : 'List of gallium drivers to build. If this is set to auto all drivers applicable to the target OS/architecture will be built'
) )
......
...@@ -71,6 +71,11 @@ static const struct drm_driver_descriptor driver_descriptors[] = { ...@@ -71,6 +71,11 @@ static const struct drm_driver_descriptor driver_descriptors[] = {
.create_screen = pipe_i915_create_screen, .create_screen = pipe_i915_create_screen,
.configuration = pipe_default_configuration_query, .configuration = pipe_default_configuration_query,
}, },
{
.driver_name = "iris",
.create_screen = pipe_iris_create_screen,
.configuration = pipe_default_configuration_query,
},
{ {
.driver_name = "nouveau", .driver_name = "nouveau",
.create_screen = pipe_nouveau_create_screen, .create_screen = pipe_nouveau_create_screen,
......
...@@ -60,6 +60,29 @@ pipe_i915_create_screen(int fd, const struct pipe_screen_config *config) ...@@ -60,6 +60,29 @@ pipe_i915_create_screen(int fd, const struct pipe_screen_config *config)
#endif #endif
#ifdef GALLIUM_IRIS
#include "iris/drm/iris_drm_public.h"
struct pipe_screen *
pipe_iris_create_screen(int fd, const struct pipe_screen_config *config)
{
struct pipe_screen *screen;
screen = iris_drm_screen_create(fd);
return screen ? debug_screen_wrap(screen) : NULL;
}
#else
struct pipe_screen *
pipe_iris_create_screen(int fd, const struct pipe_screen_config *config)
{
fprintf(stderr, "iris: driver missing\n");
return NULL;
}
#endif
#ifdef GALLIUM_NOUVEAU #ifdef GALLIUM_NOUVEAU
#include "nouveau/drm/nouveau_drm_public.h" #include "nouveau/drm/nouveau_drm_public.h"
......
...@@ -11,7 +11,7 @@ struct pipe_screen * ...@@ -11,7 +11,7 @@ struct pipe_screen *
pipe_i915_create_screen(int fd, const struct pipe_screen_config *config); pipe_i915_create_screen(int fd, const struct pipe_screen_config *config);
struct pipe_screen * struct pipe_screen *
pipe_ilo_create_screen(int fd, const struct pipe_screen_config *config); pipe_iris_create_screen(int fd, const struct pipe_screen_config *config);
struct pipe_screen * struct pipe_screen *
pipe_nouveau_create_screen(int fd, const struct pipe_screen_config *config); pipe_nouveau_create_screen(int fd, const struct pipe_screen_config *config);
......
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/*
* Copyright © 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef IRIS_BATCH_DOT_H
#define IRIS_BATCH_DOT_H
#include <stdint.h>
#include <stdbool.h>
struct iris_address {
struct iris_bo *bo;
unsigned reloc_flags;
uint32_t offset;
};
struct iris_reloc_list {
struct drm_i915_gem_relocation_entry *relocs;
int reloc_count;
int reloc_array_size;
};
struct iris_batch {
struct iris_screen *screen;
struct pipe_debug_callback *dbg;
/** Current batchbuffer being queued up. */
struct iris_bo *cmd_bo;
/** Current statebuffer being queued up. */
struct iris_bo *state_bo;
/** Last BO submitted to the hardware. Used for glFinish(). */
struct iris_bo *last_cmd_bo;
uint32_t hw_ctx_id;
void *cmd_map_next;
void *cmd_map;
void *state_map;
void *state_map_next;
bool no_wrap;
struct iris_reloc_list batch_relocs;
struct iris_reloc_list state_relocs;
/** The validation list */
struct drm_i915_gem_exec_object2 *validation_list;
struct iris_bo **exec_bos;
int exec_count;
int exec_array_size;
/** The amount of aperture space (in bytes) used by all exec_bos */
int aperture_space;
/** Map from batch offset to iris_alloc_state data (with DEBUG_BATCH) */
struct hash_table *state_sizes;
};
void iris_batch_init(struct iris_batch *batch,
struct iris_screen *screen,
struct pipe_debug_callback *dbg);
void iris_batch_free(struct iris_batch *batch);
void iris_require_command_space(struct iris_batch *batch, unsigned size);
void iris_require_state_space(struct iris_batch *batch, unsigned size);
void iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size);
void *iris_alloc_state(struct iris_batch *batch, int size, int alignment,
uint32_t *out_offset);
int _iris_batch_flush_fence(struct iris_batch *batch,
int in_fence_fd, int *out_fence_fd,
const char *file, int line);
#define iris_batch_flush_fence(batch, in_fence_fd, out_fence_fd) \
_iris_batch_flush_fence((batch), (in_fence_fd), (out_fence_fd), \
__FILE__, __LINE__)
#define iris_batch_flush(batch) iris_batch_flush_fence((batch), -1, NULL)
bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
#define RELOC_WRITE EXEC_OBJECT_WRITE
uint64_t iris_batch_reloc(struct iris_batch *batch,
uint32_t batch_offset,
struct iris_bo *target,
uint32_t target_offset,
unsigned flags);
uint64_t iris_state_reloc(struct iris_batch *batch,
uint32_t batch_offset,
struct iris_bo *target,
uint32_t target_offset,
unsigned flags);
#endif
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/*
* Copyright © 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef IRIS_CONTEXT_H
#define IRIS_CONTEXT_H
#include "pipe/p_context.h"
#include "pipe/p_state.h"
#include "util/u_debug.h"
#include "intel/common/gen_debug.h"
#include "iris_screen.h"
struct iris_bo;
#define IRIS_MAX_TEXTURE_SAMPLERS 32
#define IRIS_MAX_VIEWPORTS 16
enum iris_dirty {
IRIS_DIRTY_COLOR_CALC_STATE,
IRIS_DIRTY_POLYGON_STIPPLE,
IRIS_DIRTY_SCISSOR_RECT,
IRIS_DIRTY_WM_DEPTH_STENCIL,
};
#define IRIS_NEW_COLOR_CALC_STATE (1ull << IRIS_DIRTY_COLOR_CALC_STATE)
#define IRIS_NEW_POLYGON_STIPPLE (1ull << IRIS_DIRTY_POLYGON_STIPPLE)
#define IRIS_NEW_SCISSOR_RECT (1ull << IRIS_DIRTY_SCISSOR_RECT)
#define IRIS_NEW_WM_DEPTH_STENCIL (1ull << IRIS_DIRTY_WM_DEPTH_STENCIL)
struct iris_context {
struct pipe_context ctx;
struct pipe_debug_callback dbg;
struct {
uint64_t dirty;
struct pipe_blend_color blend_color;
struct pipe_poly_stipple poly_stipple;
struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
struct pipe_stencil_ref stencil_ref;
} state;
};
#define perf_debug(dbg, ...) do { \
if (INTEL_DEBUG & DEBUG_PERF) \
dbg_printf(__VA_ARGS__); \
if (unlikely(dbg)) \
pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \
} while(0)
double get_time(void);
struct pipe_context *
iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
void iris_init_program_functions(struct pipe_context *ctx);
void iris_init_state_functions(struct pipe_context *ctx);
#endif
/*
* Copyright © 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdio.h>
#include <errno.h>
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "pipe/p_screen.h"
#include "util/u_inlines.h"
#include "util/u_transfer.h"
#include "intel/compiler/brw_compiler.h"
#include "iris_context.h"
#define __gen_address_type unsigned
#define __gen_user_data void
static uint64_t
__gen_combine_address(void *user_data, void *location,
unsigned address, uint32_t delta)
{
return delta;
}
#define __genxml_cmd_length(cmd) cmd ## _length
#define __genxml_cmd_length_bias(cmd) cmd ## _length_bias
#define __genxml_cmd_header(cmd) cmd ## _header
#define __genxml_cmd_pack(cmd) cmd ## _pack
#define iris_pack_command(cmd, dst, name) \
for (struct cmd name = { __genxml_cmd_header(cmd) }, \
*_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
__genxml_cmd_pack(cmd)(NULL, (void *)dst, &name), \
_dst = NULL)
#define iris_pack_state(cmd, dst, name) \
for (struct cmd name = {}, \
*_dst = (void *)(dst); __builtin_expect(_dst != NULL, 1); \
__genxml_cmd_pack(cmd)(NULL, (void *)_dst, &name), \
_dst = NULL)
#include "genxml/genX_pack.h"
#include "genxml/gen_macros.h"
static void
iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
{
#if 0
l3 configuration
3DSTATE_VIEWPORT_STATE_POINTERS_CC - CC_VIEWPORT
-> from iris_depth_stencil_alpha_state
3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL - SF_CLIP_VIEWPORT
-> pipe_viewport_state for matrix elements, guardband is calculated
from those. can calculate screen space from matrix apparently...
3DSTATE_SCISSOR_STATE_POINTERS - SCISSOR_RECT
-> from ice->state.scissors
3DSTATE_PUSH_CONSTANT_ALLOC_*
3DSTATE_URB_*
-> TODO
3DSTATE_PS_BLEND
3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
-> from iris_blend_state (most) + iris_depth_stencil_alpha_state
(alpha test function/enable) + has writeable RT from ???????
3DSTATE_CC_STATE_POINTERS - COLOR_CALC_STATE
-> from ice->state.blend_color + iris_depth_stencil_alpha_state
(ref_value)
3DSTATE_CONSTANT_* - push constants
-> TODO
Surfaces:
- pull constants
- ubos/ssbos/abos
- images
- textures
- render targets - write and read
3DSTATE_BINDING_TABLE_POINTERS_*
-> TODO
3DSTATE_SAMPLER_STATE_POINTERS_*
-> TODO
3DSTATE_MULTISAMPLE
3DSTATE_SAMPLE_MASK
3DSTATE_VS
3DSTATE_HS
3DSTATE_TE
3DSTATE_DS
3DSTATE_GS
3DSTATE_PS_EXTRA
3DSTATE_PS
3DSTATE_STREAMOUT
3DSTATE_SO_BUFFER
3DSTATE_SO_DECL_LIST
3DSTATE_CLIP
-> iris_raster_state + ??? (Non-perspective Bary, ForceZeroRTAIndex)
3DSTATE_RASTER
3DSTATE_SF
-> iris_raster_state
3DSTATE_WM
-> iris_raster_state + FS state (barycentric, EDSC)
3DSTATE_SBE
-> iris_raster_state (point sprite texture coordinate origin)
-> bunch of shader state...
3DSTATE_SBE_SWIZ
-> FS state
3DSTATE_DEPTH_BUFFER
3DSTATE_HIER_DEPTH_BUFFER
3DSTATE_STENCIL_BUFFER
3DSTATE_CLEAR_PARAMS
-> iris_framebuffer_state?
3DSTATE_VF_TOPOLOGY
-> pipe_draw_info (prim_mode)
3DSTATE_VF
-> pipe_draw_info (restart_index, primitive_restart)
3DSTATE_INDEX_BUFFER
-> pipe_draw_info (index)
3DSTATE_VERTEX_BUFFERS
-> pipe_vertex_buffer (set_vertex_buffer hook)
3DSTATE_VERTEX_ELEMENTS
-> iris_vertex_element
3DSTATE_VF_INSTANCING
-> iris_vertex_element
3DSTATE_VF_SGVS
-> TODO ???
3DSTATE_VF_COMPONENT_PACKING
-> TODO ???
3DPRIMITIVE
-> pipe_draw_info
rare:
3DSTATE_POLY_STIPPLE_OFFSET
3DSTATE_POLY_STIPPLE_PATTERN
-> ice->state.poly_stipple
3DSTATE_LINE_STIPPLE
-> iris_raster_state
once:
3DSTATE_AA_LINE_PARAMETERS
3DSTATE_WM_CHROMAKEY
3DSTATE_SAMPLE_PATTERN
3DSTATE_DRAWING_RECTANGLE
3DSTATE_WM_HZ_OP
#endif
}
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/*
* Copyright © 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdio.h>
#include <errno.h>
#include "pipe/p_defines.h"
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "pipe/p_screen.h"
#include "util/u_inlines.h"
#include "util/u_format.h"
#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
#include "iris_context.h"
#include "iris_resource.h"
#include "iris_screen.h"
#include "intel/compiler/brw_compiler.h"
/**
* For debugging purposes, this returns a time in seconds.
*/
double
get_time(void)
{
struct timespec tp;
clock_gettime(CLOCK_MONOTONIC, &tp);
return tp.tv_sec + tp.tv_nsec / 1000000000.0;
}
/*
* query
*/
struct iris_query {
unsigned query;
};
static struct pipe_query *
iris_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
{
struct iris_query *query = calloc(1, sizeof(struct iris_query));
return (struct pipe_query *)query;
}
static void
iris_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
{
free(query);
}
static boolean
iris_begin_query(struct pipe_context *ctx, struct pipe_query *query)
{
return true;
}
static bool
iris_end_query(struct pipe_context *ctx, struct pipe_query *query)
{
return true;
}
static boolean
iris_get_query_result(struct pipe_context *ctx,
struct pipe_query *query,
boolean wait,
union pipe_query_result *vresult)
{
uint64_t *result = (uint64_t*)vresult;
*result = 0;
return TRUE;
}
static void
iris_set_active_query_state(struct pipe_context *pipe, boolean enable)
{
}
/*
* transfer
*/
static void *
iris_transfer_map(struct pipe_context *pipe,
struct pipe_resource *resource,
unsigned level,
enum pipe_transfer_usage usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
{
struct pipe_transfer *transfer;
struct iris_resource *res = (struct iris_resource *)resource;
transfer = calloc(1, sizeof(struct pipe_transfer));
if (!transfer)
return NULL;
pipe_resource_reference(&transfer->resource, resource);
transfer->level = level;
transfer->usage = usage;
transfer->box = *box;
transfer->stride = 1;
transfer->layer_stride = 1;
*ptransfer = transfer;
return NULL;
}
static void
iris_transfer_flush_region(struct pipe_context *pipe,
struct pipe_transfer *transfer,
const struct pipe_box *box)
{
}
static void
iris_transfer_unmap(struct pipe_context *pipe,
struct pipe_transfer *transfer)
{
pipe_resource_reference(&transfer->resource, NULL);
free(transfer);
}
static void
iris_buffer_subdata(struct pipe_context *pipe,
struct pipe_resource *resource,
unsigned usage, unsigned offset,
unsigned size, const void *data)
{
}
static void
iris_texture_subdata(struct pipe_context *pipe,
struct pipe_resource *resource,
unsigned level,
unsigned usage,
const struct pipe_box *box,
const void *data,
unsigned stride,
unsigned layer_stride)
{
}
/*
*clear/copy
*/
static void
iris_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
}
static void
iris_clear_render_target(struct pipe_context *ctx,
struct pipe_surface *dst,
const union pipe_color_union *color,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
}
static void
iris_clear_depth_stencil(struct pipe_context *ctx,
struct pipe_surface *dst,
unsigned clear_flags,
double depth,
unsigned stencil,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
}
static void
iris_resource_copy_region(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box)
{
}
static void
iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
{
}
static void
iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
{
}
/*
* context
*/
static void
iris_flush(struct pipe_context *ctx,
struct pipe_fence_handle **fence,
unsigned flags)