Commit 0d46e404 authored by Lionel Landwerlin's avatar Lionel Landwerlin

anv: limit URB reconfigurations when using blorp

If the last graphics pipeline bound to the command buffer has enough
space in its VS URB entries for Blorp then avoid reconfiguring the URB
partitions.

v2: s/0/MESA_SHADER_VERTEX/ (Caio)
Signed-off-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho's avatarCaio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
parent 84e70556
Pipeline #32004 passed with stages
in 11 minutes and 39 seconds
......@@ -2663,6 +2663,7 @@ struct anv_pipeline {
struct {
const struct gen_l3_config * l3_config;
uint32_t total_size;
unsigned entry_size[4];
} urb;
VkShaderStageFlags active_stages;
......
......@@ -202,6 +202,13 @@ blorp_emit_urb_config(struct blorp_batch *batch,
assert(sf_entry_size == 0);
/* If the last used gfx pipeline in the command buffer has enough VS URB
* space for what the blorp operation needs, skip reconfiguration.
*/
if (cmd_buffer->state.gfx.base.pipeline &&
cmd_buffer->state.gfx.base.pipeline->urb.entry_size[MESA_SHADER_VERTEX] >= vs_entry_size)
return;
const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
genX(emit_urb_setup)(device, &cmd_buffer->batch,
......
......@@ -308,18 +308,18 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
static void
emit_urb_setup(struct anv_pipeline *pipeline)
{
unsigned entry_size[4];
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
const struct brw_vue_prog_data *prog_data =
!anv_pipeline_has_stage(pipeline, i) ? NULL :
(const struct brw_vue_prog_data *) pipeline->shaders[i]->prog_data;
entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
pipeline->urb.entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
}
genX(emit_urb_setup)(pipeline->device, &pipeline->batch,
pipeline->urb.l3_config,
pipeline->active_stages, entry_size);
pipeline->active_stages,
pipeline->urb.entry_size);
}
static void
......
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