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Milestone due date
treewide: Drop nir_ssa_for_src users
!25247
· created
Sep 15, 2023
by
Alyssa Rosenzweig
Needs merge
AMD common
ANV
GLSL
NIR
RADV
Rusticl
asahi
crocus
d3d12
dozen
etnaviv
freedreno
hasvk
ir3
iris
lavapipe
lima
panfrost
r600
turnip
v3dv
zink
Merged
9
updated
Sep 18, 2023
nir: Add nir_before/after_impl cursors
!24910
· created
Aug 28, 2023
by
Alyssa Rosenzweig
Needs merge
AMD common
ANV
GLSL
NIR
RADV
SPIR-V
TGSI
asahi
crocus
d3d12
dozen
freedreno
gallium
hasvk
ir3
iris
radeon
radeonsi
vc4
zink
Merged
6
updated
Aug 30, 2023
nir: Pack is_if into parent_{instr,if}
!24671
· created
Aug 14, 2023
by
Alyssa Rosenzweig
Needs merge
ACO
AMD common
NIR
TGSI
asahi
d3d12
etnaviv
freedreno
gallium
intel-fs
ir3
lima
panfrost
r600
zink
Merged
19
updated
Oct 10, 2023
NIR 2.0
!24432
· created
Aug 01, 2023
by
Alyssa Rosenzweig
Needs review
ACO
AMD common
ANV
GLSL
NIR
Rusticl
SPIR-V
TGSI
asahi
crocus
d3d12
dozen
etnaviv
freedreno
gallium
hasvk
intel-fs
intel-vec4
ir3
iris
lima
llvmpipe
meson
nouveau
panfrost
powervr
r600
radeon
radeonsi
turnip
v3dv
vc4
vulkan
zink
Merged
4
72
updated
Oct 26, 2023
nir: Remove register arrays & indirects
!24253
· created
Jul 20, 2023
by
Alyssa Rosenzweig
Needs merge
NIR
TGSI
freedreno
gallium
intel-fs
ir3
meson
panfrost
r600
vc4
Merged
2
3
updated
Aug 03, 2023
nir: Add common load_tess_coord.z lowering
!24159
· created
Jul 14, 2023
by
Alyssa Rosenzweig
Needs merge
NIR
ir3
r600
Merged
6
updated
Jul 17, 2023
ir3: Convert to register intrinsics
!24126
· created
Jul 12, 2023
by
Alyssa Rosenzweig
Needs review
ir3
Merged
11
updated
Jul 14, 2023
nir: Remove nir_builder_init
!24038
· created
Jul 07, 2023
by
Yonggang Luo
Needs merge
AMD common
ANV
GLSL
NIR
freedreno
gallium
hasvk
ir3
r600
radeon
radeonsi
Merged
5
updated
Jul 10, 2023
nir: Teach nir_opt_preamble about control flow
!24011
· created
Jul 05, 2023
by
Alyssa Rosenzweig
Needs merge
NIR
ir3
Merged
21
updated
Oct 10, 2023
nir/lower_locals_to_regs: Add bool bitsize knob
!23804
· created
Jun 22, 2023
by
Alyssa Rosenzweig
Needs merge
NIR
gallium
intel-fs
ir3
llvmpipe
r600
Merged
13
updated
Jun 28, 2023
nir: Switch to scoped_barriers
!23191
· created
May 23, 2023
by
Alyssa Rosenzweig
Needs merge
AMD common
GLSL
NIR
SPIR-V
TGSI
gallium
ir3
radeonsi
Merged
23
updated
Jun 13, 2023
nir: Add unified atomics
!22914
· created
May 09, 2023
by
Alyssa Rosenzweig
Needs merge
ACO
AMD common
NIR
RADV
TGSI
asahi
bifrost
freedreno
ir3
llvmpipe
midgard
zink
Merged
2
111
updated
May 15, 2023
nir: Combine if_uses with instruction uses
!22343
· created
Apr 06, 2023
by
Alyssa Rosenzweig
Needs merge
NIR
TGSI
d3d12
etnaviv
freedreno
gallium
intel-fs
ir3
panfrost
vc4
Merged
4
58
updated
Jul 12, 2023
glsl/nir: Use scoped_barrier for control barrier
!21634
· created
Mar 01, 2023
by
Alyssa Rosenzweig
Needs merge
GLSL
freedreno
ir3
llvmpipe
panfrost
Merged
7
updated
Mar 07, 2023
nir/lower_tex: Add lower_index_to_offset
!21546
· created
Feb 27, 2023
by
Alyssa Rosenzweig
Needs review
NIR
bifrost
intel-fs
intel-vec4
ir3
Merged
18
updated
Mar 06, 2023
ir3: Emit barriers for images again
!13593
· created
Oct 29, 2021
by
Connor Abbott
turnip conformance
ir3
Merged
8
updated
Oct 29, 2021
ir3: Improve load_scratch/store_scratch codegen
!13307
· created
Oct 12, 2021
by
Connor Abbott
turnip conformance
ir3
turnip
Merged
7
updated
Oct 20, 2021
ir3: Bump sizes of various id's
!12487
· created
Aug 20, 2021
by
Connor Abbott
turnip conformance
ir3
turnip
Merged
7
updated
Aug 31, 2021
ir3/a6xx: account for resinfo return size dependency on IBO_0_FMT
!12485
· created
Aug 20, 2021
by
Danylo Piliaiev
turnip conformance
freedreno
ir3
turnip
Merged
7
updated
Sep 01, 2021
ir3: prohibit folding of half->full conversion into mul.s24/u24
!12471
· created
Aug 19, 2021
by
Danylo Piliaiev
turnip conformance
ir3
turnip
Merged
1
updated
Aug 20, 2021
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