diff --git a/src/etnaviv/drm/etnaviv_drmif.h b/src/etnaviv/drm/etnaviv_drmif.h index 1ad2a2e97fb9fc8f71fb397c95181ce5dc822d3f..9b492455c3ed15d8e1856c8e9be494ca231caa16 100644 --- a/src/etnaviv/drm/etnaviv_drmif.h +++ b/src/etnaviv/drm/etnaviv_drmif.h @@ -59,6 +59,10 @@ enum etna_param_id { ETNA_GPU_FEATURES_6 = 0x9, ETNA_GPU_FEATURES_7 = 0xa, ETNA_GPU_FEATURES_8 = 0xb, + ETNA_GPU_FEATURES_9 = 0xc, + ETNA_GPU_FEATURES_10 = 0xd, + ETNA_GPU_FEATURES_11 = 0xe, + ETNA_GPU_FEATURES_12 = 0xf, ETNA_GPU_STREAM_COUNT = 0x10, ETNA_GPU_REGISTER_MAX = 0x11, diff --git a/src/etnaviv/drm/etnaviv_gpu.c b/src/etnaviv/drm/etnaviv_gpu.c index 52956c415b840c3d70e3a188df286a968ab95769..31b7a32de0b4f2fd46c9d8f3efefbe340d981e6a 100644 --- a/src/etnaviv/drm/etnaviv_gpu.c +++ b/src/etnaviv/drm/etnaviv_gpu.c @@ -118,6 +118,18 @@ int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param, case ETNA_GPU_FEATURES_8: *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_8); return 0; + case ETNA_GPU_FEATURES_9: + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_9); + return 0; + case ETNA_GPU_FEATURES_10: + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_10); + return 0; + case ETNA_GPU_FEATURES_11: + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_11); + return 0; + case ETNA_GPU_FEATURES_12: + *value = get_param(dev, core, ETNAVIV_PARAM_GPU_FEATURES_12); + return 0; case ETNA_GPU_STREAM_COUNT: *value = get_param(dev, core, ETNA_GPU_STREAM_COUNT); return 0; diff --git a/src/gallium/drivers/etnaviv/etnaviv_asm.c b/src/gallium/drivers/etnaviv/etnaviv_asm.c index ab6bb4c616e70a44e5583f9f9d17ea9dc8364c75..0b6deca9b4f50b2cbf636f304d3cc785d43d6521 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_asm.c +++ b/src/gallium/drivers/etnaviv/etnaviv_asm.c @@ -65,7 +65,7 @@ etna_assemble(uint32_t *out, const struct etna_inst *inst) if (inst->imm && inst->src[2].use) return 1; - if (!inst->halti5 && !check_uniforms(inst)) + if (!inst->no_oneconst_limit && !check_uniforms(inst)) BUG("error: generating instruction that accesses two different uniforms"); assert(!(inst->opcode&~0x7f)); diff --git a/src/gallium/drivers/etnaviv/etnaviv_asm.h b/src/gallium/drivers/etnaviv/etnaviv_asm.h index 03e18a7b45a1c4f882d7207d8b3c9156c00a80ba..a0ac116b092f6e3800139f0fa03f6c062da57e96 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_asm.h +++ b/src/gallium/drivers/etnaviv/etnaviv_asm.h @@ -97,7 +97,7 @@ struct etna_inst { unsigned sel_bit0:1; /* select low half mediump */ unsigned sel_bit1:1; /* select high half mediump */ unsigned dst_full:1; /* write to highp register */ - unsigned halti5:1; /* allow multiple different uniform sources */ + unsigned no_oneconst_limit:1; /* allow multiple different uniform sources */ struct etna_inst_dst dst; /* destination operand */ struct etna_inst_tex tex; /* texture operand */ struct etna_inst_src src[ETNA_NUM_SRC]; /* source operand */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_blt.c b/src/gallium/drivers/etnaviv/etnaviv_blt.c index ec762024573d9be2624a41ab44a54766cf4082cd..87197e318350c04aabd4466103af3b880e086eb1 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_blt.c +++ b/src/gallium/drivers/etnaviv/etnaviv_blt.c @@ -450,7 +450,8 @@ etna_try_blt_blit(struct pipe_context *pctx, op.ts_clear_value[0] = src_lev->clear_value; op.ts_clear_value[1] = src_lev->clear_value; op.ts_mode = src_lev->ts_mode; - op.num_tiles = DIV_ROUND_UP(src_lev->size, src_lev->ts_mode ? 256 : 128); + op.num_tiles = DIV_ROUND_UP(src_lev->size, + etna_screen_get_tile_size(ctx->screen, src_lev->ts_mode)); op.bpp = util_format_get_blocksize(src->base.format); etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23); diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c index 4ce6d3c125c822ad80c8924a98b8aac17bb3e638..cb150749fdc71be0b00c557b2dc1412afdc939ea 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c @@ -732,7 +732,7 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader) * -insert movs (nir_lower_vec_to_movs equivalent) * for non-vecN instructions: * -try to merge constants as single constant - * -insert movs for multiple constants (pre-HALTI5) + * -insert movs for multiple constants if required */ static void lower_alu(struct etna_compile *c, nir_alu_instr *alu) @@ -749,8 +749,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu) case nir_op_vec4: break; default: - /* pre-GC7000L can only have 1 uniform src per instruction */ - if (c->specs->halti >= 5) + if (c->specs->has_no_oneconst_limit) return; nir_const_value value[4] = {}; @@ -1195,7 +1194,7 @@ etna_compile_shader(struct etna_shader_variant *v) if (inst->opcode == INST_OPCODE_BRANCH) inst->imm = block_ptr[inst->imm]; - inst->halti5 = specs->halti >= 5; + inst->no_oneconst_limit = specs->has_no_oneconst_limit; etna_assemble(&code[i * 4], inst); } diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index a433d9db9bc854ed5cc0a7022030c12377f37163..84f8697558428363fc3b2e1fdc658fa48d3a5b64 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -440,7 +440,7 @@ etna_emit_state(struct etna_context *ctx) if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE); - if (screen->specs.pixel_pipes == 1) { + if (screen->specs.halti < 0) { /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR); } @@ -477,11 +477,7 @@ etna_emit_state(struct etna_context *ctx) /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val); } if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { - if (screen->specs.pixel_pipes == 1) { - /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR); - /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); - /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); - } else if (screen->specs.pixel_pipes == 2) { + if (screen->specs.halti >= 0) { /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]); @@ -489,7 +485,9 @@ etna_emit_state(struct etna_context *ctx) /*01480*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(0), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]); /*01484*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(1), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[1]); } else { - abort(); + /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR); + /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); + /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); } } if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_ZSA))) { diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h index 36ddb3bc1ecc2f090c9338e1395b124ef630ce74..7115abced6e2e8c22ff314b2fe016137bd469acd 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h @@ -28,6 +28,8 @@ #include #include +#include "hw/common.xml.h" +#include "hw/common_3d.xml.h" #include "hw/state.xml.h" #include "hw/state_3d.xml.h" @@ -77,6 +79,8 @@ struct etna_specs { unsigned has_new_transcendentals : 1; /* has the new dp2/dpX_norm instructions, among others */ unsigned has_halti2_instructions : 1; + /* has no limit on the number of constant sources per instruction */ + unsigned has_no_oneconst_limit : 1; /* has V4_COMPRESSION */ unsigned v4_compression : 1; /* supports single-buffer rendering with multiple pixel pipes */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_nir.c b/src/gallium/drivers/etnaviv/etnaviv_nir.c index a92f96972a5026601893f47e2607c98e4f848240..6a12c6b5b9ff057da9d57738610d6e084d0e6346 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_nir.c @@ -111,7 +111,7 @@ etna_lower_io(nir_shader *shader, struct etna_shader_variant *v) case nir_tex_src_comparator: break; default: - assert(0); + //assert(0); break; } } diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c index 6f77b829151647147c4c50f9c3034513bd6b74bf..c88c04e10a4870df80bb7a0a46d441599f5a0365 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c @@ -85,8 +85,7 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen, { struct etna_screen *screen = etna_screen(pscreen); size_t rt_ts_size, ts_layer_stride; - size_t ts_bits_per_tile, bytes_per_tile; - uint8_t ts_mode = TS_MODE_128B; /* only used by halti5 */ + uint8_t ts_mode = TS_MODE_128B; int8_t ts_compress_fmt; assert(!rsc->ts_bo); @@ -98,22 +97,16 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen, ts_compress_fmt = (screen->specs.v4_compression || rsc->base.nr_samples > 1) ? translate_ts_format(rsc->base.format) : -1; - if (screen->specs.halti >= 5) { - /* enable 256B ts mode with compression, as it improves performance - * the size of the resource might also determine if we want to use it or not - */ - if (ts_compress_fmt >= 0) + /* enable 256B ts mode with compression, as it improves performance + * the size of the resource might also determine if we want to use it or not + */ + if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE) && + ts_compress_fmt >= 0) ts_mode = TS_MODE_256B; - ts_bits_per_tile = 4; - bytes_per_tile = ts_mode == TS_MODE_256B ? 256 : 128; - } else { - ts_bits_per_tile = screen->specs.bits_per_tile; - bytes_per_tile = 64; - } - ts_layer_stride = align(DIV_ROUND_UP(rsc->levels[0].layer_stride, - bytes_per_tile * 8 / ts_bits_per_tile), + etna_screen_get_tile_size(screen, ts_mode) * + 8 / screen->specs.bits_per_tile), 0x100 * screen->specs.pixel_pipes); rt_ts_size = ts_layer_stride * rsc->base.array_size; if (rt_ts_size == 0) @@ -348,7 +341,8 @@ etna_resource_create(struct pipe_screen *pscreen, layout |= ETNA_LAYOUT_BIT_MULTI; if (screen->specs.can_supertile) layout |= ETNA_LAYOUT_BIT_SUPER; - } else if (VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE) && + } else if (screen->specs.can_supertile && + VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE) && etna_resource_hw_tileable(screen->specs.use_blt, templat)) { layout |= ETNA_LAYOUT_BIT_SUPER; } diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c b/src/gallium/drivers/etnaviv/etnaviv_rs.c index c47c229a7a6d6855487508acc68474a553bad610..c2f9d02547a8069ebd221af4228b7016807bbdf6 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_rs.c +++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c @@ -78,9 +78,12 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2); unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2); - /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */ - int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1); - int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1); + bool src_tiled = rs->source_tiling & ETNA_LAYOUT_BIT_TILE; + bool dst_tiled = rs->dest_tiling & ETNA_LAYOUT_BIT_TILE; + bool src_super = rs->source_tiling & ETNA_LAYOUT_BIT_SUPER; + bool dst_super = rs->dest_tiling & ETNA_LAYOUT_BIT_SUPER; + bool src_multi = rs->source_tiling & ETNA_LAYOUT_BIT_MULTI; + bool dst_multi = rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI; /* Vivante RS needs widths to be a multiple of 16 or bad things * happen, such as scribbing over memory, or the GPU hanging, @@ -93,15 +96,19 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, cs->RS_CONFIG = VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) | COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) | COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) | - COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) | + COND(src_tiled, VIVS_RS_CONFIG_SOURCE_TILED) | VIVS_RS_CONFIG_DEST_FORMAT(rs->dest_format) | - COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) | + COND(dst_tiled, VIVS_RS_CONFIG_DEST_TILED) | COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) | COND(rs->flip, VIVS_RS_CONFIG_FLIP); cs->RS_SOURCE_STRIDE = (rs->source_stride << source_stride_shift) | - COND(rs->source_tiling & 2, VIVS_RS_SOURCE_STRIDE_TILING) | - COND(source_multi, VIVS_RS_SOURCE_STRIDE_MULTI); + COND(src_super, VIVS_RS_SOURCE_STRIDE_TILING) | + COND(src_multi, VIVS_RS_SOURCE_STRIDE_MULTI); + + if (VIV_FEATURE(ctx->screen, chipMinorFeatures6, CACHE128B256BPERLINE)) + cs->RS_SOURCE_STRIDE |= VIVS_RS_SOURCE_STRIDE_TS_MODE(rs->source_ts_mode) | + COND(src_super, VIVS_RS_SOURCE_STRIDE_SUPER_TILED_NEW); /* Initially all pipes are set to the base address of the source and * destination buffer respectively. This will be overridden below as @@ -120,14 +127,16 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, } cs->RS_DEST_STRIDE = (rs->dest_stride << dest_stride_shift) | - COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) | - COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI); + COND(dst_super, VIVS_RS_DEST_STRIDE_TILING) | + COND(dst_multi, VIVS_RS_DEST_STRIDE_MULTI); + if (VIV_FEATURE(ctx->screen, chipMinorFeatures6, CACHE128B256BPERLINE)) + cs->RS_DEST_STRIDE |= COND(dst_super, VIVS_RS_DEST_STRIDE_SUPER_TILED_NEW); - if (source_multi) + if (src_multi) cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2; - if (dest_multi) + if (dst_multi) cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2; cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) | @@ -157,7 +166,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs, rs->source_offset == rs->dest_offset && rs->source_format == rs->dest_format && rs->source_tiling == rs->dest_tiling && - (rs->source_tiling & ETNA_LAYOUT_BIT_SUPER) && + src_super && rs->source_stride == rs->dest_stride && !rs->downsample_x && !rs->downsample_y && !rs->swap_rb && !rs->flip && @@ -209,27 +218,8 @@ etna_submit_rs_state(struct etna_context *ctx, /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE); /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE); etna_coalesce_end(stream, &coalesce); - } else if (screen->specs.pixel_pipes == 1) { - etna_cmd_stream_reserve(stream, 22); - etna_coalesce_start(stream, &coalesce); - /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG); - /* 2 */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]); - /* 3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE); - /* 4 */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]); - /* 5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE); - /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE); - /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]); - /*10 */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]); - /*11 - pad */ - /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL); - /*14 */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]); - /*15 */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]); - /*16 */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]); - /*17 */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]); - /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG); - /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb); - etna_coalesce_end(stream, &coalesce); - } else if (screen->specs.pixel_pipes == 2) { + } else if (screen->specs.pixel_pipes > 1 || + VIV_FEATURE(screen, chipMinorFeatures7, RS_NEW_BASEADDR)) { etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */ etna_coalesce_start(stream, &coalesce); /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG); @@ -261,7 +251,25 @@ etna_submit_rs_state(struct etna_context *ctx, /*32/33*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb); etna_coalesce_end(stream, &coalesce); } else { - abort(); + etna_cmd_stream_reserve(stream, 22); + etna_coalesce_start(stream, &coalesce); + /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG); + /* 2 */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]); + /* 3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE); + /* 4 */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]); + /* 5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE); + /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE); + /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]); + /*10 */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]); + /*11 - pad */ + /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL); + /*14 */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]); + /*15 */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]); + /*16 */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]); + /*17 */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]); + /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG); + /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb); + etna_coalesce_end(stream, &coalesce); } } @@ -766,6 +774,7 @@ etna_try_rs_blit(struct pipe_context *pctx, .source_padded_width = src_lev->padded_width, .source_padded_height = src_lev->padded_height, .source_ts_valid = source_ts_valid, + .source_ts_mode = src_lev->ts_mode, .source_ts_compressed = src_lev->ts_compress_fmt >= 0, .dest_format = format, .dest_tiling = dst->layout, @@ -780,7 +789,8 @@ etna_try_rs_blit(struct pipe_context *pctx, .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED, .width = width, .height = height, - .tile_count = src_lev->layer_stride / 64 + .tile_count = src_lev->layer_stride / + etna_screen_get_tile_size(ctx->screen, src_lev->ts_mode), }); etna_submit_rs_state(ctx, ©_to_screen); diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.h b/src/gallium/drivers/etnaviv/etnaviv_rs.h index 748de00e16ffc524fd913d8f22869f24736ff174..5b326d396541be23e273945556ba85a2122ed120 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_rs.h +++ b/src/gallium/drivers/etnaviv/etnaviv_rs.h @@ -34,6 +34,7 @@ struct rs_state { uint8_t downsample_x : 1; /* Downsample in x direction */ uint8_t downsample_y : 1; /* Downsample in y direction */ uint8_t source_ts_valid : 1; + uint8_t source_ts_mode : 1; uint8_t source_ts_compressed : 1; uint8_t source_format; /* RS_FORMAT_XXX */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 759f65385c63e9c7d2b5263384968e365b055630..b82063f485847d828b63e4a300e56a1b5c5cc8b8 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -816,11 +816,12 @@ etna_get_specs(struct etna_screen *screen) screen->specs.can_supertile = VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); screen->specs.bits_per_tile = - VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; + !VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) || + VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE) ? 4 : 2; + screen->specs.ts_clear_value = - VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE) ? 0xffffffff : - VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 : - 0x11111111; + VIV_FEATURE(screen, chipMinorFeatures10, DEC400) ? 0xffffffff : + screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555; screen->specs.vs_need_z_div = screen->model < 0x1000 && screen->model != 0x880; @@ -836,6 +837,8 @@ etna_get_specs(struct etna_screen *screen) VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); screen->specs.has_halti2_instructions = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); + screen->specs.has_no_oneconst_limit = + VIV_FEATURE(screen, chipMinorFeatures8, SH_NO_ONECONST_LIMIT); screen->specs.v4_compression = VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION); screen->specs.seamless_cube_map = @@ -1063,6 +1066,30 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, } screen->features[8] = val; + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_9, &val)) { + DBG("could not get ETNA_GPU_FEATURES_9"); + goto fail; + } + screen->features[9] = val; + + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_10, &val)) { + DBG("could not get ETNA_GPU_FEATURES_10"); + goto fail; + } + screen->features[10] = val; + + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_11, &val)) { + DBG("could not get ETNA_GPU_FEATURES_11"); + goto fail; + } + screen->features[11] = val; + + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_12, &val)) { + DBG("could not get ETNA_GPU_FEATURES_12"); + goto fail; + } + screen->features[12] = val; + if (!etna_get_specs(screen)) goto fail; diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.h b/src/gallium/drivers/etnaviv/etnaviv_screen.h index eeac8b743ede7e44c7781e625bc582d328fef2db..3172cfd551a5729c75c194e7b1b3111887ca462e 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.h +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.h @@ -53,6 +53,11 @@ enum viv_features_word { viv_chipMinorFeatures5 = 6, viv_chipMinorFeatures6 = 7, viv_chipMinorFeatures7 = 8, + viv_chipMinorFeatures8 = 9, + viv_chipMinorFeatures9 = 10, + viv_chipMinorFeatures10 = 11, + viv_chipMinorFeatures11 = 12, + viv_chipMinorFeatures12 = 13, VIV_FEATURES_WORD_COUNT /* Must be last */ }; @@ -104,4 +109,16 @@ struct pipe_screen * etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, struct renderonly *ro); +static inline size_t +etna_screen_get_tile_size(struct etna_screen *screen, uint8_t ts_mode) +{ + if (!VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE)) + return 64; + + if (ts_mode == TS_MODE_256B) + return 256; + else + return 128; +} + #endif diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c index 1ad839799f2acd52c017ccf46c156bcba5426d1b..ffc9b741368663a0457daf9bdb4597bd7b9cd50a 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_state.c +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c @@ -159,8 +159,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cs->PE_COLOR_FORMAT |= VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK | VIVS_PE_COLOR_FORMAT_OVERWRITE | - COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) | - COND(color_supertiled && screen->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); + COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED); + if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE)) + cs->PE_COLOR_FORMAT |= COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW); /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state * but only if we set the bits above. */ @@ -176,17 +177,20 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cbuf->surf.offset, cbuf->surf.stride * 4); } - if (screen->specs.pixel_pipes == 1) { - cs->PE_COLOR_ADDR = cbuf->reloc[0]; - cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; - } else { - /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */ - assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer); + if (screen->specs.halti >= 0) { + /* Rendertargets on GPUs with more than a single pixel pipe must always + * be multi-tiled, or single-buffer mode must be supported */ + assert(screen->specs.pixel_pipes == 1 || + (res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer); for (int i = 0; i < screen->specs.pixel_pipes; i++) { cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i]; cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } + } else { + cs->PE_COLOR_ADDR = cbuf->reloc[0]; + cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } + cs->PE_COLOR_STRIDE = cbuf->surf.stride; if (cbuf->surf.ts_size) { @@ -255,14 +259,14 @@ etna_set_framebuffer_state(struct pipe_context *pctx, /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */ /* merged with depth_stencil_alpha */ - if (screen->specs.pixel_pipes == 1) { - cs->PE_DEPTH_ADDR = zsbuf->reloc[0]; - cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; - } else { + if (screen->specs.halti >= 0) { for (int i = 0; i < screen->specs.pixel_pipes; i++) { cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i]; cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } + } else { + cs->PE_DEPTH_ADDR = zsbuf->reloc[0]; + cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; } cs->PE_DEPTH_STRIDE = zsbuf->surf.stride; diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture_desc.c b/src/gallium/drivers/etnaviv/etnaviv_texture_desc.c index b9715216168d45efd619f30c0c20411a4dae4f8a..68ae15e2f90bad0e0e43523eafcfd424ec726128 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_texture_desc.c +++ b/src/gallium/drivers/etnaviv/etnaviv_texture_desc.c @@ -301,7 +301,8 @@ etna_emit_texture_desc(struct etna_context *ctx) COND(sv->ts.enable, VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE) | VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE(sv->ts.mode) | VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x)| - COND(sv->ts.comp, VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION)); + COND(sv->ts.comp, VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION) | + COND(!sv->ts.mode, VIVS_NTE_DESCRIPTOR_TX_CTRL_128B_TILE)); etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(x), SAMP_CTRL0); etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(x), ss->SAMP_CTRL1 | sv->SAMP_CTRL1); etna_set_state(stream, VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(x), ss->SAMP_LOD_MINMAX); diff --git a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h index 443649c62e705070bc0cf4bc88adb4341d9f2a3c..35922bb1f26da738cd1cdea6a7642db2b7165f71 100644 --- a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h +++ b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26877 bytes, from 2020-10-28 12:56:03) +- state.xml ( 26877 bytes, from 2022-04-09 20:48:40) - common.xml ( 35468 bytes, from 2020-10-28 12:56:03) - common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03) - state_hi.xml ( 34803 bytes, from 2020-10-28 12:56:03) - copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) - state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03) -- state_3d.xml ( 84002 bytes, from 2020-11-01 11:28:08) +- state_3d.xml ( 84326 bytes, from 2022-04-09 21:11:44) - state_blt.xml ( 14252 bytes, from 2020-10-28 12:56:03) - state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) -Copyright (C) 2012-2020 by the following authors: +Copyright (C) 2012-2022 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -982,8 +982,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK 0x00000f00 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT 8 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x) (((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK) -#define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW 0x00002000 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK 0x00001000 +#define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW 0x00002000 #define VIVS_PE_COLOR_FORMAT_OVERWRITE 0x00010000 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK 0x00020000 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED 0x00100000 @@ -1237,7 +1237,10 @@ DEALINGS IN THE SOFTWARE. #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK 0x0003ffff #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT 0 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x) (((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK) -#define VIVS_RS_SOURCE_STRIDE_UNK29 0x20000000 +#define VIVS_RS_SOURCE_STRIDE_TS_MODE__MASK 0x20000000 +#define VIVS_RS_SOURCE_STRIDE_TS_MODE__SHIFT 29 +#define VIVS_RS_SOURCE_STRIDE_TS_MODE(x) (((x) << VIVS_RS_SOURCE_STRIDE_TS_MODE__SHIFT) & VIVS_RS_SOURCE_STRIDE_TS_MODE__MASK) +#define VIVS_RS_SOURCE_STRIDE_SUPER_TILED_NEW 0x08000000 #define VIVS_RS_SOURCE_STRIDE_MULTI 0x40000000 #define VIVS_RS_SOURCE_STRIDE_TILING 0x80000000 @@ -1247,6 +1250,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_RS_DEST_STRIDE_STRIDE__MASK 0x0003ffff #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT 0 #define VIVS_RS_DEST_STRIDE_STRIDE(x) (((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK) +#define VIVS_RS_DEST_STRIDE_SUPER_TILED_NEW 0x08000000 #define VIVS_RS_DEST_STRIDE_MULTI 0x40000000 #define VIVS_RS_DEST_STRIDE_TILING 0x80000000 @@ -1789,7 +1793,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK 0x0000001c #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT 2 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK) -#define VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION 0x00000040 +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION 0x00000020 +#define VIVS_NTE_DESCRIPTOR_TX_CTRL_128B_TILE 0x00000040 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0) (0x00016000 + 0x4*(i0))