anv, iris: Emit CS Stall before Instruction Cache flush for gen12 WA
Before flushing the instruction cache with a pipe control, we need to use a CS Stall pipe control.
Ref: GEN:BUG:1409226450 Signed-off-by: Jordan Justen jordan.l.justen@intel.com
Before flushing the instruction cache with a pipe control, we need to use a CS Stall pipe control.
Ref: GEN:BUG:1409226450 Signed-off-by: Jordan Justen jordan.l.justen@intel.com