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brw: increase brw_reg::subnr size to 6 bits

Paulo Zanoni requested to merge pzanoni/mesa:brw-fix-subnr into main 
brw: increase brw_reg::subnr size to 6 bits

Since Xe2, the registers are bigger and even the instruction
structures got updated to have 6 bits.

The way I detected this issue was when I tried to use
src/intel/executor to add the following instruction:

    add(8)          g6.8<1>UD      g4<8,8,1>UD    0x00000008UD    { align1 WE_all 1Q I@1 };

Executor would read this and end up emitting an add with dst being
g6<1>UD instead of what we wanted. It turns out that inside
brw_gram.y, at dstoperand and dstoperandex we do:

    $$.subnr = $$.subnr * brw_type_size_bytes($4);

which would overflow subnr back to 0.

Fixes: e9f63df2f2c0 ("intel/dev: Enable LNL PCI IDs without INTEL_FORCE_PROBE")
Signed-off-by: Paulo Zanoni

Cc: @cmarcelo (and thanks for the help here!)

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