On Intel GPUs, shaders write outputs to a region of memory, and the next stage reads that memory as inputs. Adjacent stages need to agree on the layout. Since we look at stages independently, each one looks at inputs_read/outputs_written to decide the layout. This means that we rely on the linker to unify inputs_read/outputs_written between adjacent stages, so looking at either produces the same layout. Most of the time, cross-stage optimizations make that happen anyway, but there are some cases (with special values like clip distances) where this doesn't happen.
brw_link_shaders handles this in i965, but for iris, we need
st/nir to do it as the driver doesn't ever see multiple stages at a time. To handle this, we add a new nir shader compiler option to request this unification, and have iris set that.