brw: llvm17+ workaround update
What does this MR do and why?
brw: llvm17+ workaround update
This is a follow up to 0eb3c850c6 ("intel/clc: workaround LLVM17
opaque pointers").
Some of the generated code will have a vec4 store and a series of vec1
load after. This prevents the issue by extracting the value from the
source of the store.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Extracted from !31384