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brw: fix virtual register splitting to not go below physical register size

What does this MR do and why?

brw: fix virtual register splitting to not go below physical register size

Otherwise we can end up generating invalid assembly not following
destination/source alignments requirements.

Fixes the following tests:

dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.tan_frag
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_2.tan_frag
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.tan_frag
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_3.tan_frag

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Edited by Lionel Landwerlin

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