intel/brw: Allow register allocating g0 in more cases
!30146 (merged) recently gained us an extra register by not reserving g1 for the entirety of the program.
This continues that work by allowing g0 to be used in more cases. g0 does contain a number of critical payload fields, so it's not always available for use. But we can still do better than blanket-reserving it for the entire program.
With this series, we properly track liveness for a few use cases (scratch headers, both old and new style), then address the issue of spilling possibly introducing more uses late (by mostly bailing on the idea of using g0 there). This gains us the use of g0 in our first few schedules, where we don't allow spilling anyway (instead preferring to try less aggressive schedules before resorting to spills), making them more likely to succeed.