radeonsi/vcn: support DPB_MAX_RES on VCN5
What does this MR do and why?
radeonsi/vcn: support DPB_MAX_RES on VCN5
Use common db_alignment to calculate dpb_size for DPB_MAX_RES,
DPB_DYNAMIC_TIER_1 and DPB_DYNAMIC_TIER_2. This makes the db_pitch
in sync with all DPB types.
Remove the VCN5 hack of using 256 for H264 as 64 works.
Remove redundant codes for width and height as they were calculated
at the beginning in calc_dpb_size().
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>