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nir: Use SM5 properties to optimize shift(a, iand(31, b))

Daniel Schürmann requested to merge daniel-schuermann/mesa:shift_5bit into master

This patch optimizes a common pattern from the translation of HLSL shaders

  • shift(a, iand(0x1f, b)) -> shift(a, b) if HW supports SM5 shifts

In SM5, shift instructions are defined to use the 5 least significant bits, only, while in SPIRV shifts of 32 bits or more are undefined.
This optimization is applied late to not hinder potential future value-range optimizations of the form

  • shift(a, is_greater_31(b)) -> undef

This patch is also needed for a rework of !158 (merged) to use a different lowering for AMD as suggested.

vkpipeline-db results anv (SKL):

total instructions in shared programs: 6403130 -> 6402380 (-0.01%)
instructions in affected programs: 204084 -> 203334 (-0.37%)
helped: 208

total cycles in shared programs: 1915629582 -> 1918198408 (0.13%)
cycles in affected programs: 1158892682 -> 1161461508 (0.22%)
helped: 107
HURT: 86

Edited by Timothy Arceri

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