radv: Fix L2 cache rinse programming
According to radeonsi, GLM doesn't support WB alone, so we have to set INV too when WB is set.
Essentially, this does the same thing as the following radeonsi patch: !2109 (43e7061c)
According to radeonsi, GLM doesn't support WB alone, so we have to set INV too when WB is set.
Essentially, this does the same thing as the following radeonsi patch: !2109 (43e7061c)