aco,nir: Handle more masked_swizzle_amd special cases

GFX9 adds FFT and rotate swizzle modes (the first encounter of the new modes that I could find is in the Vega 7nm ISA documentation — GCN 3 ISA doesn't have those modes, and its documentation applies to GCN 4 too if I understand correctly; the early version of the Vega ISA documentation though changes the definition of ds_swizzle_b32 to just an undocumented opaque swizzle function, but the Vega 7nm documentation details it), don't handle them like the basic modes.

Basic mode with bit 15 set is treated as full data sharing within 4 consecutive threads.

DPP quad permutation can be used with an AND mask within a quad now without falling back to ds_swizzle on GFX8–9 or to DPP8 on GFX10+ that is slightly more limited than DPP16.

Also, since SPIR-V SwizzleInvocationsMaskedAMD explicitly accepts 3 constants containing the bit masks, thus only supporting the masked basic mode with 3 masks, don't allow invalid SPIR-V (with out-of-range masks) to produce any other modes.

I'm not sure, however, if the special modes are in the scope of the masked_swizzle_amd intrinsic overall — if it was designed specifically for the 3 masks, maybe this new code is not needed (since I can't find any place where those special modes are emitted in Mesa, it's pretty much reserved for future now with this commit, to prepare the safety measures in case we actually use those modes), but if it's just a direct wrapper of ds_swizzle_b32, full coverage of the possible argument ranges is needed.

The original purpose of this commit, however, was to simply allow the AND mask to be used in the implementation based on DPP16 quad permutations, as long as it's still limited to the current quad.

I haven't tested this beyond just launching some random apps though, but if you can recommend which tests I should run, I'll check if nothing has regressed — unfortunately I'm not yet able to build the Vulkan CTS because of some weird error about the .git/index target needed for qphelper.