intel: Headerless MRT on Gen11+
Gen11 adds support for specifying the render target index and src0 alpha present bits in the extended message descriptor. Previously, we had to use a message header for this, requiring extra instructions to write the fields, and two registers of extra payload.
Improves performance in a few things (using iris):
- GfxBench5 Manhattan 3.0: 2.13635% +/- 0.159859% (n=5)
- GfxBench5 Aztec Ruins: 1.57173% +/- 0.128749% (n=5)
- Synmark2 OglDeferred: 2.86914% +/- 0.191211% (n=10)