Draft: nir: Import nir_lower_mem_width from brw

From the active patch:

This pass lowers unsupported, "wide" memory accesses to a sequence of smaller
accesses. It's required for OpenCL, which can load/store up to 1024-bits in a
single instruction (u64vec16). In practice, (almost?) no hardware can support
such a wide load, thus some version of this pass is necessary for any backend
that wants to support OpenCL. Currently Iris is the only NIR driver that's
capable of passing the CL CTS, so let's use Intel's implementation as the
starting point.

The pass is renamed from brw_nir_lower_mem_access_bit_sizes to
nir_lower_mem_width for consistency with nir_lower_alu_width which does
basically the same thing for a different instruction type.

Note: this is just moving the code, it does not yet change the logic. At this
point, this pass bakes in some pretty Intel-specific assumptions. However, the
code itself is generic and can live in NIR. The next patches will lift these
Intel assumptions to make it suitable for other drivers.

I want this pass for OpenCL on Valhall. I imagine it's needed for OpenCL on any hardware driver, though. Draft because I didn't actually do the part where I generalize it of brwisms (e.g. the special case for scratch memory), adding appropriate driver callbacks. But I wanted to open the MR so I don't forget about it can get some feedback from other NIR/OpenCL and Intel stakeholders on whether this pass is the right solution to the vec16 64 ssa_5 = load_global problem with OpenCL.