From da7a7c9bbc7f582a5aa433f70be10078b9d0301f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Wed, 20 Jul 2022 12:30:32 +0300 Subject: [PATCH 1/2] iris: implement Wa_14015264727 for DG2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On DG2 we need to flush data cache before fast clear operation. Signed-off-by: Tapani Pälli Reviewed-by: Kenneth Graunke Part-of: --- src/gallium/drivers/iris/iris_clear.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 16387b43aa5a..6391fdb50479 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -254,6 +254,11 @@ fast_clear_color(struct iris_context *ice, * and again afterwards to ensure that the resolve is complete before we * do any more regular drawing. */ + + /* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */ + bool data_cache_flush_needed = + intel_device_info_is_dg2(&batch->screen->devinfo); + iris_emit_end_of_pipe_sync(batch, "fast clear: pre-flush", PIPE_CONTROL_RENDER_TARGET_FLUSH | @@ -262,6 +267,8 @@ fast_clear_color(struct iris_context *ice, PIPE_CONTROL_DEPTH_STALL : 0) | (devinfo->verx10 == 125 ? PIPE_CONTROL_FLUSH_HDC : 0) | + (data_cache_flush_needed ? + PIPE_CONTROL_DATA_CACHE_FLUSH : 0) | PIPE_CONTROL_PSS_STALL_SYNC); iris_batch_sync_region_start(batch); -- GitLab From a6857ee43e4907a7b65332a27dadf19095bf53f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Wed, 20 Jul 2022 15:29:22 +0300 Subject: [PATCH 2/2] anv: implement Wa_14015264727 for DG2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On DG2 we need to flush data cache before fast clear operation. Signed-off-by: Tapani Pälli Reviewed-by: Kenneth Graunke Part-of: --- src/intel/vulkan/anv_blorp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 6dab9036ea1d..7cc5e885d556 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1852,6 +1852,11 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, * resolve and then use a second PIPE_CONTROL after the resolve to ensure * that it is completed before any additional drawing occurs. */ + + /* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */ + bool data_cache_flush_needed = + intel_device_info_is_dg2(&cmd_buffer->device->info); + anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT | @@ -1859,6 +1864,8 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_DEPTH_STALL_BIT : 0) | (devinfo->verx10 == 125 ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0) | + (data_cache_flush_needed ? + ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) | ANV_PIPE_PSS_STALL_SYNC_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT, "before fast clear mcs"); -- GitLab