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lima/ppir: fix alignment on regalloc spilling loads

Erico Nunes requested to merge enunes/mesa:lima-ppir-regalloc-spill-align into master

The ppir spilling code spills entire vec4 registers regardless of the components used by the spilled uses. The inserted stores code force the 4 components, but these loads were using a variable number of components, causing bugs on loading the spilled registers.

Also fixed related regalloc debug strings on a separate commit.

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