From e6d262a7fab7a8090556f7c178f2ece5b52d1147 Mon Sep 17 00:00:00 2001 From: Gert Wollny Date: Sun, 17 Apr 2022 17:22:27 +0200 Subject: [PATCH 1/4] virgl: Clear all indirect flags when writing to a temporary The output may be an array, e.g. with a TCS shader, so if the value is written to a temporaray first remove the indirect indicator for that write. Fixes: 36f12c85c84364d7f1ea797512462e7c7e47a260 virgl: Extend integer write out output fix to all non-move integers ops Signed-off-by: Gert Wollny Reviewed-by: Gert Wollny Part-of: --- src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt | 1 - src/gallium/drivers/virgl/virgl_tgsi.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt b/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt index adfb44353e39..9f425522d318 100644 --- a/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt +++ b/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt @@ -681,7 +681,6 @@ spec@arb_tessellation_shader@execution@gs-primitiveid-instanced,Fail spec@arb_tessellation_shader@execution@tcs-tes-levels-out-of-bounds-write,Crash spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-dvec4-index-rd,Fail -spec@arb_tessellation_shader@execution@variable-indexing@tcs-tes-array-in-struct,Fail spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-dvec4-index-wr,Fail spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-dvec4-index-rd,Fail spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-dvec4-index-wr-before-tcs,Fail diff --git a/src/gallium/drivers/virgl/virgl_tgsi.c b/src/gallium/drivers/virgl/virgl_tgsi.c index aa755b58ddd8..a707a246a407 100644 --- a/src/gallium/drivers/virgl/virgl_tgsi.c +++ b/src/gallium/drivers/virgl/virgl_tgsi.c @@ -393,6 +393,8 @@ virgl_tgsi_transform_instruction(struct tgsi_transform_context *ctx, struct tgsi_full_instruction op_to_temp = *inst; op_to_temp.Dst[0].Register.File = TGSI_FILE_TEMPORARY; op_to_temp.Dst[0].Register.Index = vtctx->src_temp; + op_to_temp.Dst[0].Dimension.Indirect = 0; + op_to_temp.Dst[0].Register.Indirect = 0; ctx->emit_instruction(ctx, &op_to_temp); inst->Instruction.Opcode = TGSI_OPCODE_MOV; -- GitLab From 4205039a9f3c928ec059df0331a36846b3a6caa2 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Fri, 8 Apr 2022 12:24:22 -0700 Subject: [PATCH 2/4] nir_to_tgsi: Lower FS input array indexing since we don't declare input arrays. We can't declare input arrays because mesa/st lowers NIR VS output declarations to elements no matter what, and virgl has depended on matching array sizes of declarations between producers and consumers. So, we have to lower it away (which is fine because hardware drivers will generally be lowering anyway). Reviewed-by: Gert Wollny Part-of: --- src/gallium/auxiliary/nir/nir_to_tgsi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index d0ca7f5fc86d..8ddbf8a250c7 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -3743,6 +3743,18 @@ const void *nir_to_tgsi_options(struct nir_shader *s, ntt_fix_nir_options(screen, s, options); + /* Lower array indexing on FS inputs. Since we don't set + * ureg->supports_any_inout_decl_range, the TGSI input decls will be split to + * elements by ureg, and so dynamically indexing them would be invalid. + * Ideally we would set that ureg flag based on + * PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, but can't due to mesa/st + * splitting NIR VS outputs to elements even if the FS doesn't get the + * corresponding splitting, and virgl depends on TGSI across link boundaries + * having matching declarations. + */ + if (s->info.stage == MESA_SHADER_FRAGMENT) + NIR_PASS_V(s, nir_lower_indirect_derefs, nir_var_shader_in, UINT32_MAX); + NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size, (nir_lower_io_options)0); NIR_PASS_V(s, nir_lower_regs_to_ssa); -- GitLab From 337b3dabc0ee1b31343e76a316f4d0443552650d Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Tue, 19 Apr 2022 16:21:02 -0700 Subject: [PATCH 3/4] tgsi: Extend array lengths when merging usage_masks. With nir-to-tgsi, virgl saw a case where a previous declaration of array .x and scalar .y (turning into an array with .xy) ended up being a declaration of scalar .x and array .y (turning into a scalar with .xy). Make sure we extend the declared array length as well. One might think that the fix would be to union the .first/.last between the two declarations being merged, but note that ureg_DECL_output() passes in the current nr_output_regs as the index, so the .last would end up getting extended for those callers (such as nir_to_tgsi fs outputs) every time you merged. Reviewed-by: Gert Wollny Part-of: --- src/gallium/auxiliary/tgsi/tgsi_ureg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c index 76c1bd9f47fa..398d59b957b3 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c +++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c @@ -308,6 +308,8 @@ ureg_DECL_fs_input_centroid_layout(struct ureg_program *ureg, assert(ureg->input[i].interp_location == interp_location); if (ureg->input[i].array_id == array_id) { ureg->input[i].usage_mask |= usage_mask; + ureg->input[i].last = MAX2(ureg->input[i].last, ureg->input[i].first + array_size - 1); + ureg->nr_input_regs = MAX2(ureg->nr_input_regs, ureg->input[i].last + 1); goto out; } assert((ureg->input[i].usage_mask & usage_mask) == 0); @@ -445,6 +447,8 @@ ureg_DECL_output_layout(struct ureg_program *ureg, ureg->output[i].semantic_index == semantic_index) { if (ureg->output[i].array_id == array_id) { ureg->output[i].usage_mask |= usage_mask; + ureg->output[i].last = MAX2(ureg->output[i].last, ureg->output[i].first + array_size - 1); + ureg->nr_output_regs = MAX2(ureg->nr_output_regs, ureg->output[i].last + 1); goto out; } assert((ureg->output[i].usage_mask & usage_mask) == 0); -- GitLab From c5cc9ed29b50ada77f875ad0d999678021678922 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Mon, 20 Dec 2021 16:31:54 -0800 Subject: [PATCH 4/4] virgl: Switch to nir-to-tgsi by default. With !8044 all TGSI drivers will end up going through the nir-to-tgsi path, so make the switch now that CI is happy (which will also make sure that future NTT work doesn't break virgl). Reviewed-by: Gert Wollny Reviewed-by: Timothy Arceri Part-of: --- src/gallium/drivers/virgl/ci/traces-virgl.yml | 16 +- .../drivers/virgl/ci/virgl-gl-skips.txt | 10 + .../drivers/virgl/ci/virpipe-gl-fails.txt | 318 ++---------------- .../drivers/virgl/ci/virpipe-gl-flakes.txt | 3 + src/gallium/drivers/virgl/virgl_screen.c | 8 +- src/gallium/drivers/virgl/virgl_screen.h | 2 +- 6 files changed, 61 insertions(+), 296 deletions(-) diff --git a/src/gallium/drivers/virgl/ci/traces-virgl.yml b/src/gallium/drivers/virgl/ci/traces-virgl.yml index ac1d02b34308..7258277b1b56 100644 --- a/src/gallium/drivers/virgl/ci/traces-virgl.yml +++ b/src/gallium/drivers/virgl/ci/traces-virgl.yml @@ -9,7 +9,7 @@ traces: - path: glmark2/jellyfish.trace expectations: - device: gl-virgl - checksum: 1873b70a28539825879b530477cf6d27 + checksum: 48a2ad1162bf92301cedbe53edf52a6b - path: glxgears/glxgears-2.trace expectations: - device: gl-virgl @@ -17,11 +17,11 @@ traces: - path: gputest/furmark.trace expectations: - device: gl-virgl - checksum: a38d4c123d13c5ccd3a86f0663fe1aab + checksum: 6e498eb959f7da847eb6d2cbbfaea5d5 - path: gputest/pixmark-piano.trace expectations: - device: gl-virgl - checksum: b580ae01560380461a103975cab77393 + checksum: 33770ade1aed893528c597f63af892f2 - path: gputest/triangle.trace expectations: - device: gl-virgl @@ -33,7 +33,7 @@ traces: - path: 0ad/0ad.trace expectations: - device: gl-virgl - checksum: 5e5bd83446d2554bf25761576d9b1af6 + checksum: 5e8f945ba7316a70a5195c1c23d35809 - path: glmark2/buffer:update-fraction=0.5:update-dispersion=0.9:columns=200:update-method=map:interleave=false.trace expectations: - device: gl-virgl @@ -77,7 +77,7 @@ traces: - path: glmark2/effect2d:kernel=0,1,0;1,-4,1;0,1,0;.trace expectations: - device: gl-virgl - checksum: 25d3b5d18a64a86fc812872987f4f5e7 + checksum: 35584880539813436d87bfcbe22cf59b - path: glmark2/effect2d:kernel=1,1,1,1,1;1,1,1,1,1;1,1,1,1,1;.trace expectations: - device: gl-virgl @@ -174,11 +174,11 @@ traces: - path: gputest/pixmark-volplosion.trace expectations: - device: gl-virgl - checksum: 9bedb84d81528e1b4087522de9f70383 + checksum: 0c7aab484c251b0f90745ced620bed82 - path: gputest/plot3d.trace expectations: - device: gl-virgl - checksum: 7e818a6070005056700e5ef8590a3f8e + checksum: 2915192067704d738cdc4c2eaa88a2b1 # Times out # - path: gputest/tessmark.trace # expectations: @@ -246,7 +246,7 @@ traces: - path: supertuxkart/supertuxkart-mansion-egl-gles.trace expectations: - device: gl-virgl - checksum: 5e4e0cedd57bedf3eb7f127489a46b12 + checksum: b93f2d23cc42072eff674829094cbe74 - path: xonotic/xonotic-keybench-high.trace expectations: - device: gl-virgl diff --git a/src/gallium/drivers/virgl/ci/virgl-gl-skips.txt b/src/gallium/drivers/virgl/ci/virgl-gl-skips.txt index 4061d4ef47cb..4c3e6f27fa9d 100644 --- a/src/gallium/drivers/virgl/ci/virgl-gl-skips.txt +++ b/src/gallium/drivers/virgl/ci/virgl-gl-skips.txt @@ -4,3 +4,13 @@ # Sometimes crashes, e.g. https://gitlab.freedesktop.org/kusma/mesa/-/jobs/4109419 dEQP-GLES31.functional.compute.basic.empty + +# too slow. +dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36 +dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.22 + +# Since switching to NIR-to-TGSI, this one is a little too slow in LLVM in +# virglrenderer and virgl ends up timing out waiting for it. +dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.22 + +KHR-GL.*.texture_swizzle.smoke diff --git a/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt b/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt index 9f425522d318..482c4b79f74d 100644 --- a/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt +++ b/src/gallium/drivers/virgl/ci/virpipe-gl-fails.txt @@ -41,7 +41,6 @@ dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_x,Fail KHR-GL43.compute_shader.fp64-case1,Fail -KHR-GL43.compute_shader.fp64-case3,Fail KHR-GL43.compute_shader.resource-subroutine,Fail KHR-GL43.cull_distance.functional,Fail KHR-GL43.gpu_shader_fp64.fp64.named_uniform_blocks,Fail @@ -75,7 +74,14 @@ KHR-GL43.shader_storage_buffer_object.advanced-usage-sync,Fail KHR-GL43.shader_storage_buffer_object.basic-atomic-case1,Fail KHR-GL43.shader_storage_buffer_object.basic-atomic-case2,Fail KHR-GL43.shader_subroutine.ssbo_atomic_image_load_store,Fail + +# virglrenderer translates TGSI IMAGE declaration "WR" ("image is not readonly") +# into the writeonly qualifier, which works for gles (where each image is either +# RO or WO) but not for desktop GL. +KHR-GL43.shading_language_420pack.binding_image_array,Fail + KHR-GL43.shading_language_420pack.binding_images,Fail +KHR-GL43.shading_language_420pack.length_of_vector_and_matrix,Fail KHR-GL43.texture_view.view_sampling,Fail KHR-GL43.transform_feedback_overflow_query_ARB.advanced-single-stream-interleaved-attribs,Fail KHR-GL43.transform_feedback_overflow_query_ARB.advanced-single-stream-separate-attribs,Fail @@ -110,8 +116,10 @@ glx@glx_ext_import_context@make current- multi process,Fail glx@glx_ext_import_context@make current- single process,Fail glx@glx_ext_import_context@query context info,Fail +# https://gitlab.freedesktop.org/mesa/mesa/-/issues/6362 shaders@glsl-uniform-interstage-limits@subdivide 5- statechanges,Fail shaders@glsl-uniform-interstage-limits@subdivide 5,Fail + shaders@point-vertex-id divisor,Fail shaders@point-vertex-id gl_instanceid,Fail shaders@point-vertex-id gl_instanceid divisor,Fail @@ -123,9 +131,12 @@ spec@!opengl 1.0@gl-1.0-dlist-bitmap,Fail spec@!opengl 1.0@gl-1.0-edgeflag,Fail spec@!opengl 1.0@gl-1.0-edgeflag-quads,Fail spec@!opengl 1.0@gl-1.0-swapbuffers-behavior,Fail -spec@!opengl 1.0@rasterpos,Fail + +# https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10641 +spec@!opengl 1.0@rasterpos,Crash spec@!opengl 1.0@rasterpos@glsl_vs_gs_linked,Fail spec@!opengl 1.0@rasterpos@glsl_vs_tes_linked,Fail + spec@!opengl 1.1@depthstencil-default_fb-copypixels,Fail spec@!opengl 1.1@depthstencil-default_fb-copypixels samples=2,Fail spec@!opengl 1.1@depthstencil-default_fb-copypixels samples=4,Fail @@ -355,8 +366,7 @@ spec@arb_depth_texture@texwrap formats bordercolor@GL_DEPTH_COMPONENT16- border spec@arb_depth_texture@texwrap formats bordercolor@GL_DEPTH_COMPONENT24- border color only,Fail spec@arb_depth_texture@texwrap formats bordercolor@GL_DEPTH_COMPONENT32- border color only,Fail spec@arb_direct_state_access@gettextureimage-formats init-by-rendering,Fail -spec@arb_enhanced_layouts@execution@component-layout@vs-fs-array-dvec3,Fail -spec@arb_enhanced_layouts@execution@component-layout@vs-to-fs-array-interleave-single-location,Fail + spec@arb_es2_compatibility@texwrap formats bordercolor,Fail spec@arb_es2_compatibility@texwrap formats bordercolor-swizzled,Fail spec@arb_es2_compatibility@texwrap formats bordercolor-swizzled@GL_RGB565- swizzled- border color only,Fail @@ -372,13 +382,6 @@ spec@arb_get_texture_sub_image@arb_get_texture_sub_image-getcompressed,Crash spec@arb_gpu_shader5@execution@precise@fs-fract-of-nan,Fail -# "./src/gallium/auxiliary/tgsi/tgsi_ureg.h:893: ureg_src ureg_swizzle(ureg_src, int, int, int, int): Assertion `reg.File != TGSI_FILE_NULL' failed." -spec@arb_gpu_shader5@execution@samplemaskin-out-of-bounds,Crash - -# segfault -spec@arb_gpu_shader5@execution@sampler_array_indexing@array-of-sampler-2d-array-out-of-bounds-access,Crash -spec@arb_gpu_shader5@execution@sampler_array_indexing@array-of-sampler-2d-out-of-bounds-access,Crash - spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dmat2x4-mat2x4,Fail @@ -418,155 +421,24 @@ spec@arb_gpu_shader_fp64@execution@conversion@vert-conversion-explicit-double-fl spec@arb_gpu_shader_fp64@execution@conversion@vert-conversion-explicit-dvec2-vec2,Fail spec@arb_gpu_shader_fp64@execution@conversion@vert-conversion-explicit-dvec3-vec3,Fail spec@arb_gpu_shader_fp64@execution@conversion@vert-conversion-explicit-dvec4-vec4,Fail -spec@arb_gpu_shader_fp64@execution@fs-double-uniform-array-direct-indirect-non-uniform-control-flow,Fail -spec@arb_gpu_shader_fp64@execution@fs-function-inout-array,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-dvec3@2@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-float-and-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat3x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat4x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat4x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dmat4x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-double-float-double@2-float@3-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-double@3-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-double@3@2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-double@4-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec2@3-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec2@4-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec3@2@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec3@2@2-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec3@3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-dvec3@4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-double@3@2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-float-float-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-float-float-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float-float-float-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@1-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@1-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@1-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@1-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@1-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@2-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@3-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@4-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@5-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@5-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@5-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@5-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@5-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@6-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@6-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@6-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@6-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-float@6-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2-double-s3-float-s4-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2-float-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2-s3@2-float-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2-s3@2-vec3-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2-vec2-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2-vec3-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2@2-float-double,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2@2-float-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2@2-vec2-double,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2@2-vec2-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2@2-vec3-double,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@2@2-vec3-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@3-double-float-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@3-dvec2-float-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-s2@3-dvec3-float-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-double@3@2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec2-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dmat2x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dmat2x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dmat2x4-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dmat3x2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dmat3x3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-double@3@2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dvec2-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1-vec3-dvec3-location-0,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s1@2-s2@2-s3@2-double-location-0,Crash -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s2@2@2-float-double,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s2@2@2-vec2-double,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-s2@2@2-vec3-double,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-vec2-and-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@inout@vs-out-fs-in-vec3-and-double@3@2,Fail -spec@arb_gpu_shader_fp64@execution@vs-double-uniform-array-direct-indirect-non-uniform-control-flow,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@fs-array-copy,Fail + spec@arb_gpu_shader_fp64@uniform_buffers@fs-dmat4,Fail spec@arb_gpu_shader_fp64@uniform_buffers@fs-dmat4-row-major,Fail spec@arb_gpu_shader_fp64@uniform_buffers@fs-double-array-const-index,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@fs-double-uniform-array-direct-indirect,Fail spec@arb_gpu_shader_fp64@uniform_buffers@fs-doubles,Fail spec@arb_gpu_shader_fp64@uniform_buffers@fs-doubles-float-mixed,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@fs-dvec4-uniform-array-direct-indirect,Fail spec@arb_gpu_shader_fp64@uniform_buffers@fs-nested-struct,Fail spec@arb_gpu_shader_fp64@uniform_buffers@fs-ubo-direct-1,Fail spec@arb_gpu_shader_fp64@uniform_buffers@gs-dmat4,Fail spec@arb_gpu_shader_fp64@uniform_buffers@gs-dmat4-row-major,Fail spec@arb_gpu_shader_fp64@uniform_buffers@gs-double-array-const-index,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@gs-double-uniform-array-direct-indirect,Fail spec@arb_gpu_shader_fp64@uniform_buffers@gs-doubles-float-mixed,Fail spec@arb_gpu_shader_fp64@uniform_buffers@gs-nested-struct,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@vs-array-copy,Fail spec@arb_gpu_shader_fp64@uniform_buffers@vs-dmat4,Fail spec@arb_gpu_shader_fp64@uniform_buffers@vs-dmat4-row-major,Fail spec@arb_gpu_shader_fp64@uniform_buffers@vs-double-array-const-index,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@vs-double-uniform-array-direct-indirect,Fail spec@arb_gpu_shader_fp64@uniform_buffers@vs-doubles,Fail spec@arb_gpu_shader_fp64@uniform_buffers@vs-doubles-float-mixed,Fail -spec@arb_gpu_shader_fp64@uniform_buffers@vs-dvec4-uniform-array-direct-indirect,Fail spec@arb_gpu_shader_fp64@uniform_buffers@vs-nested-struct,Fail spec@arb_occlusion_query@occlusion_query_conform,Fail spec@arb_occlusion_query@occlusion_query_conform@GetObjivAval_multi1,Fail @@ -576,19 +448,12 @@ spec@arb_point_sprite@arb_point_sprite-mipmap,Fail spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex,Fail spec@arb_program_interface_query@arb_program_interface_query-getprogramresourceindex@'vs_input2[1][0]' on GL_PROGRAM_INPUT,Fail -# "exit status: signal: 13" -spec@arb_shader_atomic_counter_ops@execution@atomic-counter-array-out-of-bounds-access,Crash - spec@arb_shader_atomic_counters@fragment-discard,Fail spec@arb_sample_shading@builtin-gl-sample-position 2,Fail spec@arb_shader_image_load_store@early-z,Fail spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail -# segfault -spec@arb_shader_image_load_store@execution@image-array-out-of-bounds-access-load,Crash -spec@arb_shader_image_load_store@execution@image-array-out-of-bounds-access-store,Crash - spec@arb_shader_image_load_store@layer,Fail spec@arb_shader_image_load_store@layer@image2DMS/layered binding test,Fail spec@arb_shader_image_load_store@layer@image2DMS/non-layered binding test,Fail @@ -677,13 +542,11 @@ spec@arb_tessellation_shader@execution@dvec2-vs-tcs-tes,Fail spec@arb_tessellation_shader@execution@dvec3-vs-tcs-tes,Fail spec@arb_tessellation_shader@execution@gs-primitiveid-instanced,Fail -# "../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:3355: virtual void glsl_to_tgsi_visitor::visit(ir_assignment*): Assertion `!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector()' failed." +# " intrinsic copy_deref (ssa_2, ssa_3) (dst_access=0, src_access=0) +# error: glsl_get_bare_type(dst->type) == glsl_get_bare_type(src->type) (../src/compiler/nir/nir_validate.c:643)" +# since ntt copy-deref optimization, probably. spec@arb_tessellation_shader@execution@tcs-tes-levels-out-of-bounds-write,Crash -spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-dvec4-index-rd,Fail -spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-dvec4-index-wr,Fail -spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-dvec4-index-rd,Fail -spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-dvec4-index-wr-before-tcs,Fail spec@arb_texture_buffer_object@formats (fs- arb),Crash spec@arb_texture_buffer_object@formats (fs- arb)@GL_LUMINANCE16I_EXT,Fail spec@arb_texture_buffer_object@formats (fs- arb)@GL_LUMINANCE16UI_EXT,Fail @@ -996,23 +859,26 @@ spec@ext_texture_srgb@texwrap formats-s3tc bordercolor@GL_COMPRESSED_SRGB_ALPHA_ spec@ext_texture_srgb@texwrap formats-s3tc bordercolor@GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT- border color only,Fail spec@ext_texture_srgb@texwrap formats-s3tc bordercolor@GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT- border color only,Fail spec@ext_texture_srgb@texwrap formats-s3tc bordercolor@GL_COMPRESSED_SRGB_S3TC_DXT1_EXT- border color only,Fail + spec@glsl-1.10@execution@samplers@glsl-fs-shadow1d-07,Fail spec@glsl-1.10@execution@samplers@glsl-fs-shadow1d-08,Fail spec@glsl-1.10@execution@samplers@glsl-fs-shadow2d-07,Fail spec@glsl-1.10@execution@samplers@glsl-fs-shadow2d-08,Fail spec@glsl-1.10@execution@samplers@glsl-fs-shadow2d-clamp-z,Fail spec@glsl-1.20@compiler@invalid-vec4-array-to-vec3-array-conversion.vert,Fail -spec@glsl-1.20@execution@matrix-out-of-bounds-access@fs-mat4-out-of-bounds-6,Crash -# segfaults -spec@glsl-1.30@execution@clipping@vs-clip-distance-out-of-bounds-access-read,Crash -spec@glsl-1.30@execution@clipping@vs-clip-distance-out-of-bounds-access-write,Crash - -# "exit status: signal: 13" +# "ERROR - Piglit error: NIR validation failed after nir_lower_locals_to_regs" +# "ERROR - Piglit error: error: (src->reg.reg->num_array_elems == 0 || src->reg.base_offset < src->reg.reg->num_array_elems) && "definitely out-of-bounds array access" (../src/compiler/nir/nir_validate.c:174)" +spec@glsl-1.30@execution@fs-large-local-array-out-of-bounds-read,Crash spec@glsl-1.30@execution@fs-large-local-array-out-of-bounds-write,Crash +spec@glsl-1.30@execution@vs-isnan-and-more-comparison,Fail + spec@glsl-1.50@execution@primitive-id-no-gs-quad-strip,Fail spec@glsl-1.50@execution@primitive-id-no-gs-quads,Fail + +spec@glsl-1.50@execution@variable-indexing@gs-input-array-float-index-rd,Fail + spec@glsl-4.00@execution@conversion@frag-conversion-explicit-dmat2-mat2,Fail spec@glsl-4.00@execution@conversion@frag-conversion-explicit-dmat2x3-mat2x3,Fail spec@glsl-4.00@execution@conversion@frag-conversion-explicit-dmat2x4-mat2x4,Fail @@ -1052,128 +918,7 @@ spec@glsl-4.00@execution@conversion@vert-conversion-explicit-double-float,Fail spec@glsl-4.00@execution@conversion@vert-conversion-explicit-dvec2-vec2,Fail spec@glsl-4.00@execution@conversion@vert-conversion-explicit-dvec3-vec3,Fail spec@glsl-4.00@execution@conversion@vert-conversion-explicit-dvec4-vec4,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-dvec3@2@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-float-and-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat3x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat4x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat4x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dmat4x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-double-float-double@2-float@3-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-double@3-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-double@3@2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-double@4-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec2@3-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec2@4-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec3@2@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec3@2@2-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec3@3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-dvec3@4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-double@3@2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-float-float-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-float-float-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float-float-float-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@1-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@1-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@1-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@1-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@1-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@2-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@3-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@4-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@5-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@5-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@5-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@5-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@5-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@6-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@6-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@6-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@6-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-float@6-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2-double-s3-float-s4-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2-float-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2-s3@2-float-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2-s3@2-vec3-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2-vec2-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2-vec3-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2@2-float-double,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2@2-float-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2@2-vec2-double,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2@2-vec2-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2@2-vec3-double,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@2@2-vec3-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@3-double-float-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@3-dvec2-float-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-s2@3-dvec3-float-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-double@3@2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec2-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dmat2x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dmat2x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dmat2x4-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dmat3x2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dmat3x3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-double@3@2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dvec2-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1-vec3-dvec3-location-0,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s1@2-s2@2-s3@2-double-location-0,Crash -spec@glsl-4.00@execution@inout@vs-out-fs-in-s2@2@2-float-double,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s2@2@2-vec2-double,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-s2@2@2-vec3-double,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-vec2-and-double@3@2,Fail -spec@glsl-4.00@execution@inout@vs-out-fs-in-vec3-and-double@3@2,Fail + spec@khr_texture_compression_astc@array-gl,Fail spec@khr_texture_compression_astc@array-gl@12x12 Block Dim,Fail spec@khr_texture_compression_astc@array-gl@5x5 Block Dim,Fail @@ -1208,6 +953,13 @@ spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb,Fail spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb@sRGB decode,Fail + +spec@nv_copy_depth_to_color@nv_copy_depth_to_color,Fail +spec@nv_copy_depth_to_color@nv_copy_depth_to_color 0 0x223344ff,Fail +spec@nv_copy_depth_to_color@nv_copy_depth_to_color 0 0x76356278,Fail +spec@nv_copy_depth_to_color@nv_copy_depth_to_color 1 0x223344ff,Fail +spec@nv_copy_depth_to_color@nv_copy_depth_to_color 1 0x76356278,Fail + spec@nv_copy_image@nv_copy_image-formats,Fail spec@nv_copy_image@nv_copy_image-formats@Source: GL_COMPRESSED_RED_RGTC1/Destination: GL_COMPRESSED_RED_RGTC1,Fail spec@nv_copy_image@nv_copy_image-formats@Source: GL_COMPRESSED_RGBA_BPTC_UNORM/Destination: GL_COMPRESSED_RGBA_BPTC_UNORM,Fail diff --git a/src/gallium/drivers/virgl/ci/virpipe-gl-flakes.txt b/src/gallium/drivers/virgl/ci/virpipe-gl-flakes.txt index 58c4117753c9..dc6c1eee5207 100644 --- a/src/gallium/drivers/virgl/ci/virpipe-gl-flakes.txt +++ b/src/gallium/drivers/virgl/ci/virpipe-gl-flakes.txt @@ -31,6 +31,9 @@ spec@arb_shader_atomic_counter_ops@execution@atomic-counter-array-out-of-bounds- spec@arb_shader_atomic_counters@fragment-discard spec@arb_shader_atomic_counters@function-argument +spec@arb_shader_image_load_store@execution@image-array-out-of-bounds-access-load +spec@arb_shader_image_load_store@execution@image-array-out-of-bounds-access-store + spec@arb_shader_storage_buffer_object@execution@memory-layouts-struct-deref spec@arb_shader_storage_buffer_object@execution@ssbo-atomicadd-int spec@arb_shader_storage_buffer_object@execution@ssbo-atomicexchange-int diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index 17f9b58a7a17..455f71d96507 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -46,7 +46,7 @@ int virgl_debug = 0; static const struct debug_named_value virgl_debug_options[] = { { "verbose", VIRGL_DEBUG_VERBOSE, NULL }, { "tgsi", VIRGL_DEBUG_TGSI, NULL }, - { "nir", VIRGL_DEBUG_NIR, NULL }, + { "use_tgsi", VIRGL_DEBUG_USE_TGSI, NULL }, { "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA, "Disable tweak to emulate BGRA as RGBA on GLES hosts"}, { "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" }, { "sync", VIRGL_DEBUG_SYNC, "Sync after every flush" }, @@ -437,9 +437,9 @@ virgl_get_shader_param(struct pipe_screen *screen, else return vscreen->caps.caps.v2.max_shader_image_other_stages; case PIPE_SHADER_CAP_PREFERRED_IR: - return (virgl_debug & VIRGL_DEBUG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; + return (virgl_debug & VIRGL_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR; case PIPE_SHADER_CAP_SUPPORTED_IRS: - return (1 << PIPE_SHADER_IR_TGSI) | ((virgl_debug & VIRGL_DEBUG_NIR) ? (1 << PIPE_SHADER_IR_NIR) : 0); + return (1 << PIPE_SHADER_IR_TGSI) | ((virgl_debug & VIRGL_DEBUG_USE_TGSI) ? 0 : (1 << PIPE_SHADER_IR_NIR)); case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: return vscreen->caps.caps.v2.max_atomic_counters[shader]; case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: @@ -961,7 +961,7 @@ static void virgl_disk_cache_create(struct virgl_screen *screen) _mesa_sha1_init(&sha1_ctx); _mesa_sha1_update(&sha1_ctx, id_sha1, build_id_len); - uint32_t shader_debug_flags = virgl_debug & VIRGL_DEBUG_NIR; + uint32_t shader_debug_flags = virgl_debug & VIRGL_DEBUG_USE_TGSI; _mesa_sha1_update(&sha1_ctx, &shader_debug_flags, sizeof(shader_debug_flags)); uint8_t sha1[20]; diff --git a/src/gallium/drivers/virgl/virgl_screen.h b/src/gallium/drivers/virgl/virgl_screen.h index 90bcaba8846c..cbebb8d422ab 100644 --- a/src/gallium/drivers/virgl/virgl_screen.h +++ b/src/gallium/drivers/virgl/virgl_screen.h @@ -37,7 +37,7 @@ enum virgl_debug_flags { VIRGL_DEBUG_SYNC = 1 << 4, VIRGL_DEBUG_XFER = 1 << 5, VIRGL_DEBUG_NO_COHERENT = 1 << 6, - VIRGL_DEBUG_NIR = 1 << 7, + VIRGL_DEBUG_USE_TGSI = 1 << 7, VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK = 1 << 8, }; -- GitLab