It's finally here, the next installment in the ir3 register allocation saga. With pvtmem support and the RA rewrite landed, this is "just" a matter of implementing a spilling pass in the style of "Register Spilling and Live-Range Splitting for SSA-Form Programs." The spilling pass is actually more-or-less an extension of the register pressure accounting pass, which is already in
ir3_spill.c, and the last commit basically rewrites
ir3_spill.c so that it actually spills.
I've done the following testing:
- All the tests in CI marked as failing due to
ir3_ra. All of these pass.
- Some graphicsfuzz tests which also fail. These now pass, except for
dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-compositewhich sometimes times out on my device (HDK865).
- All of
dEQP-VK.graphicsfuzz.*(except the aforementioned graphicsfuzz test) with
IR3_SHADER_DEBUG=spillall, which tries to calculate the minimum possible pressure below which spilling would choke and then uses that as the pressure limit for spilling.
There are, however, still some loose ends:
- This needs to be integrated with the
max_waveslogic to figure out the register pressure limit for compute shaders with a barrier.
- There are a number of optimizations that could be made. Most notable is rematerialization. There are also improvements still to do around loops, and around parallel copy handling. I optimized pcopy handling a bit in an attempt to optimize
dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-composite, but there are still some TODO's there.
- We need to implement spilling shared registers to normal registers. I think that this can't be integrated into the spilling pass here and will need its own pass instead, due to weirdness with shared registers.
Closes: #33 (closed)