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iris: Reduce SSBO alignment requirements from 64B to 4B

Kenneth Graunke requested to merge kwg/mesa:ic-ssbo-align into main

Back when SSBOs were first enabled in i965, we tried to work around issues where the CPU and GPU were incoherently writing to the same cacheline by forcing an alignment such that different sections of data would fall in different cachelines. This seems wrong.

On integrated GPUs with LLC, CPU and GPU writes should be coherent. On integrated GPUs without LLC, we either enable snooping (so they are again coherent), or we use WC maps (so the CPU cache isn't used). Discrete GPUs always use WC maps (so the CPU cache isn't used).

This should work. In other words, I think the increased alignment was just working around coherency problems on atoms that have been fixed in the intervening 6 year time period.

Untyped surface messages require 4B alignment, and I believe typed surface messages should be fine with that as well.

Closes: #5016 (closed)

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