diff --git a/src/freedreno/ci/deqp-freedreno-a630-fails.txt b/src/freedreno/ci/deqp-freedreno-a630-fails.txt
index 2ec1dd70f655cca57a643885f6dc52a08fcd792f..0c212d57db55fa37921b0fe1502173ea15a59c3a 100644
--- a/src/freedreno/ci/deqp-freedreno-a630-fails.txt
+++ b/src/freedreno/ci/deqp-freedreno-a630-fails.txt
@@ -152,36 +152,11 @@ dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.denor
 dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.denorm_nmax_denorm_preserve_vert,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.denorm_nmin_denorm_preserve_frag,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.float_controls.fp32.input_args.denorm_nmin_denorm_preserve_vert,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_bit_geom,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_bit_tessc,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_frag,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_tesse,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.carry_to_exponent_vert,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_frag,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_tesse,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_round_up_or_round_down_vert,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_too_small_frag,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_too_small_tesse,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.negative_too_small_vert,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_round_up_or_round_down_geom,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.positive_round_up_or_round_down_tessc,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_frag,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_tesse,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_inf_vert,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_negative_inf_geom,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.opquantize.round_to_negative_inf_tessc,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_bit_geom,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_bit_tessc,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_frag,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_tesse,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_carry_to_exponent_vert,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_frag,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_tesse,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_negative_round_up_or_round_down_vert,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_positive_round_up_or_round_down_geom,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.spec_const_positive_round_up_or_round_down_tessc,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.too_small_geom,Fail
-dEQP-VK.spirv_assembly.instruction.graphics.opquantize.too_small_tessc,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_single_buffer_geom,Fail
 dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_two_buffers_geom,Fail
 dEQP-VK.spirv_assembly.instruction.spirv1p4.opcopylogical.nested_arrays_different_inner_stride,Fail
diff --git a/src/freedreno/ir3/ir3_cf.c b/src/freedreno/ir3/ir3_cf.c
index d479bc10759b01fc188fa224fa0bc364c4cdbfc2..0ede500baa20abbb3da6c1cd9daea5d71c76e9b5 100644
--- a/src/freedreno/ir3/ir3_cf.c
+++ b/src/freedreno/ir3/ir3_cf.c
@@ -21,6 +21,18 @@
  * SOFTWARE.
  */
 
+/**
+ * @file ir3_cf.c
+ *
+ * Folds f2f32(16-bit) operations into the generating ALU instruction when all
+ * uses ofthe ALU instr are an f2f32.
+ *
+ * Note that we can't fold f2f16(32-bit) operations into the generating ALU
+ * instruction because for SpvOpQuantize we need an f2f32(f2f16(x)) to actually
+ * do a conversion to 16-bit.  If it's valid to elide that conversion (in GLSL),
+ * it should already have happened at the NIR level.
+ */
+
 #include "util/ralloc.h"
 
 #include "ir3.h"
@@ -49,10 +61,6 @@ is_fp16_conv(struct ir3_instruction *instr)
 			instr->cat1.dst_type == TYPE_F16)
 		return true;
 
-	if (instr->cat1.src_type == TYPE_F16 &&
-			instr->cat1.dst_type == TYPE_F32)
-		return true;
-
 	return false;
 }
 
@@ -102,12 +110,6 @@ try_conversion_folding(struct ir3_instruction *conv)
 	if (!is_alu(src))
 		return false;
 
-	/* avoid folding f2f32(f2f16) together, in cases where this is legal to
-	 * do (glsl) nir should have handled that for us already:
-	 */
-	if (is_fp16_conv(src))
-		return false;
-
 	switch (src->opc) {
 	case OPC_SEL_B32:
 	case OPC_SEL_B16: