From b26a546b2f828990c109e3fae991b5cf50c4ffdd Mon Sep 17 00:00:00 2001 From: Simon Ser Date: Fri, 9 Apr 2021 10:18:44 +0200 Subject: [PATCH 1/5] radeon/vcn: handle tiled buffers when decoding Set the swizzle mode when decoding. Add a safe-guard to make sure the provided surface isn't DCC, because we don't handle this situation. Signed-off-by: Leo Liu Signed-off-by: Simon Ser Reviewed-by: Leo Liu Part-of: --- src/gallium/drivers/radeon/radeon_vcn_dec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c index 312934d19e9b..310eb9aadf6d 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c @@ -1651,8 +1651,13 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec, decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; decode->dt_uv_pitch = decode->dt_pitch / 2; + if (luma->surface.meta_offset) { + RVID_ERR("DCC surfaces not supported.\n"); + return NULL; + } + decode->dt_tiling_mode = 0; - decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR; + decode->dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode; decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR; decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced; decode->dt_surf_tile_config = 0; -- GitLab From 6e697b595f8a46348a41be673a37bc0a39a8e032 Mon Sep 17 00:00:00 2001 From: Simon Ser Date: Fri, 9 Apr 2021 13:54:28 +0200 Subject: [PATCH 2/5] util/format: document block depth field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After the pixel block width and height, a third field is used to store the pixel block depth. Document this field. Signed-off-by: Simon Ser Reviewed-by: Marek Olšák Acked-by: Leo Liu Part-of: --- src/util/format/u_format.csv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/util/format/u_format.csv b/src/util/format/u_format.csv index cab28847abab..8cb7e88de2fd 100644 --- a/src/util/format/u_format.csv +++ b/src/util/format/u_format.csv @@ -34,6 +34,7 @@ # - layout, per enum util_format_layout, in shortened lower caps # - pixel block's width # - pixel block's height +# - pixel block's depth, in number of pixels # - channel encoding (only meaningful for plain layout), containing for each # channel the following information: # - type, one of -- GitLab From 19378dfe3c2a27ab2f9ed737d5553306233faf30 Mon Sep 17 00:00:00 2001 From: Simon Ser Date: Fri, 9 Apr 2021 13:58:40 +0200 Subject: [PATCH 3/5] ac/surface: use blocksizebits instead of blocksize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit util_format_get_blocksize asserts that the blocksize isn't zero. However the blocksize will be zero if the format's channel encoding is unspecified. The channel encoding is only meaningful for the plain u_format layout, so util_format_get_blocksize can't be used for formats with another layout. For example, YUV formats don't have the channel encoding specified. Use util_format_get_blocksizebits, which just returns zero without an assertion for formats which don't have a channel encoding. Signed-off-by: Simon Ser Reviewed-by: Marek Olšák Acked-by: Leo Liu Part-of: --- src/amd/common/ac_surface.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 5ef3a0d7e849..b4274c880a28 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -185,7 +185,7 @@ bool ac_is_modifier_supported(const struct radeon_info *info, if (util_format_is_compressed(format) || util_format_is_depth_or_stencil(format) || - util_format_get_blocksize(format) > 8) + util_format_get_blocksizebits(format) > 64) return false; if (info->chip_class < GFX9) @@ -276,7 +276,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, common_dcc | AMD_FMT_MOD_SET(PIPE, pipes)) - if (util_format_get_blocksize(format) == 4) { + if (util_format_get_blocksizebits(format) == 32) { if (info->max_render_backends == 1) { ADD_MOD(AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | @@ -365,7 +365,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) | AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits)) - if (util_format_get_blocksize(format) != 4) { + if (util_format_get_blocksizebits(format) != 32) { ADD_MOD(AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9)); -- GitLab From 979e13869538e79e8b56e18dfb4e7ea8816443f4 Mon Sep 17 00:00:00 2001 From: Simon Ser Date: Fri, 9 Apr 2021 14:03:53 +0200 Subject: [PATCH 4/5] radeonsi: stop special-casing YUV formats in si_query_dmabuf_modifiers Instead of having a special case for YUV formats in si_query_dmabuf_modifiers, let ac_get_supported_modifiers handle them. Keep setting external_only = 1 for YUV formats, since we can only sample from such formats (we can't use them as render targets). This shouldn't change si_query_dmabuf_modifiers's behavior, because for YUV formats ac_get_supported_modifiers will return a single LINEAR modifier. Signed-off-by: Simon Ser Reviewed-by: Bas Nieuwenhuizen Acked-by: Leo Liu Part-of: --- src/gallium/drivers/radeonsi/si_texture.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index c54cf2d9f45c..50621e0ed8c1 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1341,16 +1341,6 @@ static void si_query_dmabuf_modifiers(struct pipe_screen *screen, { struct si_screen *sscreen = (struct si_screen *)screen; - if (util_format_is_yuv(format)) { - if (max) { - *modifiers = DRM_FORMAT_MOD_LINEAR; - if (external_only) - *external_only = 1; - } - *count = 1; - return; - } - unsigned ac_mod_count = max; ac_get_supported_modifiers(&sscreen->info, &(struct ac_modifier_options) { .dcc = !(sscreen->debug_flags & DBG(NO_DCC)), @@ -1361,7 +1351,7 @@ static void si_query_dmabuf_modifiers(struct pipe_screen *screen, }, format, &ac_mod_count, max ? modifiers : NULL); if (max && external_only) { for (unsigned i = 0; i < ac_mod_count; ++i) - external_only[i] = 0; + external_only[i] = util_format_is_yuv(format); } *count = ac_mod_count; } -- GitLab From 35e25ea1d07c5af7ec99c65db06010338af369aa Mon Sep 17 00:00:00 2001 From: Simon Ser Date: Fri, 9 Apr 2021 14:07:29 +0200 Subject: [PATCH 5/5] ac/surface: allow non-DCC modifiers for YUV on GFX9+ Accept non-linear tiling for multi-planar formats on GFX9+, as long as DCC is disabled. DCC support is possible in theory, but untested for now. GFX8 is still restricted to linear tiling because it's not yet clear how modifiers should be handled on these chips for multi-planar formats. Each plane may need a different modifier. Signed-off-by: Simon Ser Reviewed-by: Bas Nieuwenhuizen Acked-by: Leo Liu Part-of: --- src/amd/common/ac_surface.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index b4274c880a28..b24a75919450 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -194,7 +194,8 @@ bool ac_is_modifier_supported(const struct radeon_info *info, if(modifier == DRM_FORMAT_MOD_LINEAR) return true; - if (util_format_get_num_planes(format) > 1) + /* GFX8 may need a different modifier for each plane */ + if (info->chip_class < GFX9 && util_format_get_num_planes(format) > 1) return false; uint32_t allowed_swizzles = 0xFFFFFFFF; @@ -214,6 +215,10 @@ bool ac_is_modifier_supported(const struct radeon_info *info, return false; if (ac_modifier_has_dcc(modifier)) { + /* TODO: support multi-planar formats with DCC */ + if (util_format_get_num_planes(format) > 1) + return false; + if (!info->has_graphics) return false; -- GitLab