mesa merge requestshttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests2024-02-27T09:24:30Zhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27814tu: tu_device should clean up its global bo2024-02-27T09:24:30ZZan Dobersektu: tu_device should clean up its global bo### What does this MR do and why?
<!-- Describe in detail what your merge request does and why. -->
```
tu: tu_device should clean up its global bo
The global buffer object is allocated and mapped during tu_device creation.
Correspondi...### What does this MR do and why?
<!-- Describe in detail what your merge request does and why. -->
```
tu: tu_device should clean up its global bo
The global buffer object is allocated and mapped during tu_device creation.
Correspondingly it should also be cleaned up during device destruction.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
```https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27783clover: drop support for nir drivers2024-02-26T14:52:55ZKarol Herbstkherbst@redhat.comclover: drop support for nir driversDevelopment basically is non existent and it allows for some clean ups and space savings.
afaik there are no reasons to not do this. This also drops `PIPE_SHADER_IR_NIR_SERIALIZED` which is something that shouldn't have been added in th...Development basically is non existent and it allows for some clean ups and space savings.
afaik there are no reasons to not do this. This also drops `PIPE_SHADER_IR_NIR_SERIALIZED` which is something that shouldn't have been added in the first place.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10674https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27775tu: wideLines support for a7xx.2024-02-26T10:18:03ZAmber Harmoniatu: wideLines support for a7xx.Support wideLines on a7xx, passes CTS and custom tests.
Passing `dEQP-VK.clipping.clip_volume.clipped.wide_lines_*`Support wideLines on a7xx, passes CTS and custom tests.
Passing `dEQP-VK.clipping.clip_volume.clipped.wide_lines_*`https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27526vulkan: Fix some file names and include paths2024-02-23T10:05:52ZYonggang Luovulkan: Fix some file names and include paths### What does this MR do and why?
<!-- Describe in detail what your merge request does and why. -->
```
radv,nvk: Remove vulkan/runtime prefix in include path
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
```### What does this MR do and why?
<!-- Describe in detail what your merge request does and why. -->
```
radv,nvk: Remove vulkan/runtime prefix in include path
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
```https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27483freedreno: add support for a7xx perfcounters2024-02-26T08:51:45ZZan Dobersekfreedreno: add support for a7xx perfcountersThese changes add support for perfcounters on a7xx. There's enough differences between a6xx and a7xx hwblocks, counter registers and lists of countables that a separate `fd7_perfcntr.c` implementation file makes sense.These changes add support for perfcounters on a7xx. There's enough differences between a6xx and a7xx hwblocks, counter registers and lists of countables that a separate `fd7_perfcntr.c` implementation file makes sense.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27482Draft: freedreno: missing a6xx performance counters, countables2024-02-06T15:55:14ZZan DobersekDraft: freedreno: missing a6xx performance counters, countablesThis starts as a sort of RFC: there are some additional perfcounter groups as well as countables for existing groups that could be included.
Current changes:
- add a perfcounter group for the CMP hwblock,
- add additional PERF_UCHE coun...This starts as a sort of RFC: there are some additional perfcounter groups as well as countables for existing groups that could be included.
Current changes:
- add a perfcounter group for the CMP hwblock,
- add additional PERF_UCHE countables,
- add additional PERF_SP countables.
There's other additional groups that could finally be added if they are of interest and functioning properly, e.g. for the RBBM and VBIF blocks.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27462freedreno, turnip, ir3: Early preamble2024-02-16T17:28:06ZConnor Abbottfreedreno, turnip, ir3: Early preambleIn addition to introducing the scalar ALU, in a650 a copy of the scalar ALU and some other units were added to the HLSQ, which dispatches work to the uSPTPs (shader cores), and it can now execute the preamble part of shaders "early," i.e...In addition to introducing the scalar ALU, in a650 a copy of the scalar ALU and some other units were added to the HLSQ, which dispatches work to the uSPTPs (shader cores), and it can now execute the preamble part of shaders "early," i.e. before work is dispatched, rather than as part of the first wave dispatched to each uSPTP. This can help hide the latency of executing the preamble. Traditionally, the HLSQ also prefetched various state via the `CP_LOAD_STATE` packet, but recently more and more of this functionality has been moving to the preamble, with the implicit expectation that it is executed in an early preamble:
- Since a730 shared consts (Vulkan push constants) are setup in the preamble.
- Since a730 descriptors are prefetched in the preamble.
- Since a750 `CP_LOAD_STATE` to setup constants is now deprecated and severely limited, so most driver params come from UBOs that are pushed to the constant file in a preamble.
As more and more things are being executed in the preamble, hiding the latency becomes more important.
We can't always execute a preamble early. Early preambles cannot have "normal" (i.e. not shared) registers or predicate registers (so they cannot have control flow). If the preamble contains these, then we have to fall back to using it as a normal "late" preamble.
This MR implements early preamble, based on !22075 which implements the scalar ALU. While this doesn't actually depend on that series, without scalar ALU the cases we can use early preamble are severly limited.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27411ir3: improve handling of predicate registers2024-02-27T17:30:39ZJob Noormanir3: improve handling of predicate registersThis series improves the handling of predicate registers in ir3 by doing a few things:
- Make use if all four predicate registers available since a6xx by adding a register allocator for them. Up to now, only a single register (`p0.x`) wa...This series improves the handling of predicate registers in ir3 by doing a few things:
- Make use if all four predicate registers available since a6xx by adding a register allocator for them. Up to now, only a single register (`p0.x`) was used. The new RA also works for older gens with only one predicate register.
- Add codegen for the new `braa`/`brao` instructions available since a6xx by folding and/or into them.
- Folding negations into branches using the `inv1`/`inv2` fields (all gens).
- Make bitwise operations directly write to predicate registers which is possible since a6xx.
- Add CSE for `cmps`.
# ir3 core changes
To make this all possible/easier to implement, some core changes to ir3 were made.
Instead of using `brtype` and `condition` fields in blocks, explicitly add terminator branches in their instruction lists. This makes it more uniform to deal with branches in passes. This is especially useful for passes that need to deal with predicate registers like the new register allocator.
We currently have a bit of a confusing situation where we have both opcodes for the different branches (`OPC_BR`, `OPC_BRAA`,...) and branch types which are supposed to be used with `OPC_B` (`BRANCH_PLAIN`, `BRANCH_AND`,...). However, not every kind of branch has a corresponding type. For example, `getone` is represented by `OPC_GETONE` instead of a branch type.
This series proposes to get rid of the branch types and use opcodes everywhere. I think this makes the representation of branches more consistent. It also removes the for the encoder to translate branch types into opcodes.
# Predicate register allocation
Because predicate registers can be "spilled" (see below) to GPRs, the predicate RA is implemented as a pass before regular RA.
The RA uses the standard liveness analysis available in ir3. Using this, registers are allocated in a single pass over all blocks. For each block we keep track of currently live defs in the registers. Predicate destinations allocate a new register and sources take the register from their def.
The live defs of a block are initialized with the intersection of the live-out defs of their predecessors: if all predecessors have the same live-out def in the same register, it is used as live-in. However, we only do this for defs that are actually live-in according to the liveness analysis.
This doesn't work for loops: since predecessors from back edges are processed after their successors, we don't know their live-out state yet. We solve this by ignoring such predecessors while calculating the live-in state. When this predecessor is later processed, we fix-up its live-out state to match what its successor expects by reloading defs if necessary.
Spilling is implemented by reloading, or rematerializing, the instruction that produced the def. Whenever we need a new register while none are available, we simply free one. If the freed def is later needed again, we clone the original instruction in front on the new use. We keep track of the original def the reload is cloned from so that subsequent uses can reuse the reload. Note that this essentially spills the predicate register to the GPR sources of the cloned instruction.
# Optimize bitwise operations
When generating instructions that need a predicate source, ir3 will insert a `cmps.s.ne 0` instruction to guarantee a predicate can be produced. We add a pass that removes those`cmps`s whenever their source is a bitwise operation that can directly write to a predicate register.
# Folding and/or/not into branches
Fold and/or into `braa`/`brao` when profitable. Only do this when the and/or is not used for any non-branch instructions as this would increase total instruction count.
Add an algebraic nir pass that performs the inverse DeMorgan's laws to try to bring and/or in front of branches. Again, only do this when the original inot in only used for branches. This should always decrease instruction count since the extra inots can be folded into the branch.
# Results
<details>
<summary>a540 shader-db including Rob's shaders</summary>
<pre>
total instructions in shared programs: 3427644 -> 3419435 (-0.24%)
instructions in affected programs: 467758 -> 459549 (-1.75%)
helped: 958
HURT: 46
helped stats (abs) min: 1 max: 512 x̄: 8.74 x̃: 7
helped stats (rel) min: 0.15% max: 20.97% x̄: 2.83% x̃: 2.39%
HURT stats (abs) min: 1 max: 18 x̄: 3.65 x̃: 1
HURT stats (rel) min: 0.11% max: 13.33% x̄: 1.22% x̃: 0.53%
95% mean confidence interval for instructions value: -9.24 -7.12
95% mean confidence interval for instructions %-change: -2.80% -2.50%
Instructions are helped.
total nops in shared programs: 601486 -> 595384 (-1.01%)
nops in affected programs: 113378 -> 107276 (-5.38%)
helped: 903
HURT: 129
helped stats (abs) min: 1 max: 384 x̄: 7.15 x̃: 6
helped stats (rel) min: 0.67% max: 30.00% x̄: 8.10% x̃: 8.57%
HURT stats (abs) min: 1 max: 21 x̄: 2.72 x̃: 1
HURT stats (rel) min: 0.26% max: 81.82% x̄: 4.93% x̃: 3.25%
95% mean confidence interval for nops value: -6.70 -5.13
95% mean confidence interval for nops %-change: -6.91% -6.04%
Nops are helped.
total non-nops in shared programs: 2826158 -> 2824051 (-0.07%)
non-nops in affected programs: 355752 -> 353645 (-0.59%)
helped: 1023
HURT: 0
helped stats (abs) min: 1 max: 128 x̄: 2.06 x̃: 1
helped stats (rel) min: 0.14% max: 19.15% x̄: 1.08% x̃: 0.60%
95% mean confidence interval for non-nops value: -2.32 -1.79
95% mean confidence interval for non-nops %-change: -1.15% -1.00%
Non-nops are helped.
total mov in shared programs: 248303 -> 248225 (-0.03%)
mov in affected programs: 532 -> 454 (-14.66%)
helped: 19
HURT: 1
helped stats (abs) min: 1 max: 7 x̄: 4.16 x̃: 4
helped stats (rel) min: 1.89% max: 66.67% x̄: 21.38% x̃: 16.67%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00%
95% mean confidence interval for mov value: -5.01 -2.79
95% mean confidence interval for mov %-change: -28.19% -9.94%
Mov are helped.
total cov in shared programs: 101693 -> 101692 (<.01%)
cov in affected programs: 26 -> 25 (-3.85%)
helped: 1
HURT: 0
total dwords in shared programs: 6877604 -> 6871258 (-0.09%)
dwords in affected programs: 383250 -> 376904 (-1.66%)
helped: 414
HURT: 10
helped stats (abs) min: 2 max: 512 x̄: 15.59 x̃: 6
helped stats (rel) min: 0.13% max: 25.00% x̄: 3.31% x̃: 1.46%
HURT stats (abs) min: 2 max: 32 x̄: 11.00 x̃: 4
HURT stats (rel) min: 0.16% max: 4.92% x̄: 1.62% x̃: 0.94%
95% mean confidence interval for dwords value: -17.59 -12.35
95% mean confidence interval for dwords %-change: -3.63% -2.76%
Dwords are helped.
total last-baryf in shared programs: 97405 -> 97398 (<.01%)
last-baryf in affected programs: 384 -> 377 (-1.82%)
helped: 4
HURT: 4
helped stats (abs) min: 1 max: 22 x̄: 7.25 x̃: 3
helped stats (rel) min: 1.67% max: 15.71% x̄: 11.16% x̃: 13.64%
HURT stats (abs) min: 1 max: 10 x̄: 5.50 x̃: 5
HURT stats (rel) min: 3.03% max: 27.03% x̄: 15.03% x̃: 15.03%
95% mean confidence interval for last-baryf value: -9.23 7.48
95% mean confidence interval for last-baryf %-change: -12.45% 16.31%
Inconclusive result (value mean confidence interval includes 0).
total last-helper in shared programs: 1372136 -> 1368491 (-0.27%)
last-helper in affected programs: 159566 -> 155921 (-2.28%)
helped: 305
HURT: 39
helped stats (abs) min: 1 max: 512 x̄: 12.38 x̃: 8
helped stats (rel) min: 0.15% max: 21.31% x̄: 3.53% x̃: 2.79%
HURT stats (abs) min: 1 max: 18 x̄: 3.36 x̃: 1
HURT stats (rel) min: 0.11% max: 13.46% x̄: 1.26% x̃: 0.40%
95% mean confidence interval for last-helper value: -13.67 -7.52
95% mean confidence interval for last-helper %-change: -3.31% -2.67%
Last-helper are helped.
total half in shared programs: 62509 -> 62147 (-0.58%)
half in affected programs: 826 -> 464 (-43.83%)
helped: 345
HURT: 0
helped stats (abs) min: 1 max: 16 x̄: 1.05 x̃: 1
helped stats (rel) min: 4.35% max: 100.00% x̄: 75.17% x̃: 100.00%
95% mean confidence interval for half value: -1.14 -0.96
95% mean confidence interval for half %-change: -78.80% -71.55%
Half are helped.
total full in shared programs: 173294 -> 173271 (-0.01%)
full in affected programs: 89 -> 66 (-25.84%)
helped: 6
HURT: 2
helped stats (abs) min: 3 max: 9 x̄: 4.50 x̃: 4
helped stats (rel) min: 25.00% max: 42.86% x̄: 32.14% x̃: 33.33%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for full value: -5.85 0.10
95% mean confidence interval for full %-change: -43.74% 20.53%
Inconclusive result (value mean confidence interval includes 0).
total constlen in shared programs: 879612 -> 879612 (0.00%)
constlen in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat0 in shared programs: 660130 -> 654028 (-0.92%)
cat0 in affected programs: 120305 -> 114203 (-5.07%)
helped: 903
HURT: 129
helped stats (abs) min: 1 max: 384 x̄: 7.15 x̃: 6
helped stats (rel) min: 0.65% max: 26.09% x̄: 7.44% x̃: 7.89%
HURT stats (abs) min: 1 max: 21 x̄: 2.72 x̃: 1
HURT stats (rel) min: 0.25% max: 54.55% x̄: 4.03% x̃: 3.03%
95% mean confidence interval for cat0 value: -6.70 -5.13
95% mean confidence interval for cat0 %-change: -6.37% -5.65%
Cat0 are helped.
total cat1 in shared programs: 355780 -> 355697 (-0.02%)
cat1 in affected programs: 1188 -> 1105 (-6.99%)
helped: 20
HURT: 1
helped stats (abs) min: 1 max: 7 x̄: 4.20 x̃: 4
helped stats (rel) min: 1.32% max: 66.67% x̄: 14.67% x̃: 7.14%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 16.67% max: 16.67% x̄: 16.67% x̃: 16.67%
95% mean confidence interval for cat1 value: -5.09 -2.81
95% mean confidence interval for cat1 %-change: -22.03% -4.32%
Cat1 are helped.
total cat2 in shared programs: 1233203 -> 1231179 (-0.16%)
cat2 in affected programs: 181622 -> 179598 (-1.11%)
helped: 1010
HURT: 0
helped stats (abs) min: 1 max: 128 x̄: 2.00 x̃: 1
helped stats (rel) min: 0.25% max: 18.18% x̄: 2.37% x̃: 1.14%
95% mean confidence interval for cat2 value: -2.27 -1.74
95% mean confidence interval for cat2 %-change: -2.55% -2.19%
Cat2 are helped.
total cat3 in shared programs: 1031422 -> 1031422 (0.00%)
cat3 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat4 in shared programs: 75629 -> 75629 (0.00%)
cat4 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat5 in shared programs: 47992 -> 47992 (0.00%)
cat5 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat6 in shared programs: 22498 -> 22498 (0.00%)
cat6 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat7 in shared programs: 990 -> 990 (0.00%)
cat7 in affected programs: 0 -> 0
helped: 0
HURT: 0
total stp in shared programs: 2 -> 2 (0.00%)
stp in affected programs: 0 -> 0
helped: 0
HURT: 0
total ldp in shared programs: 2 -> 2 (0.00%)
ldp in affected programs: 0 -> 0
helped: 0
HURT: 0
total sstall in shared programs: 247837 -> 248330 (0.20%)
sstall in affected programs: 6810 -> 7303 (7.24%)
helped: 31
HURT: 122
helped stats (abs) min: 1 max: 10 x̄: 3.71 x̃: 1
helped stats (rel) min: 1.59% max: 17.86% x̄: 6.37% x̃: 5.26%
HURT stats (abs) min: 1 max: 75 x̄: 4.98 x̃: 3
HURT stats (rel) min: 0.80% max: 115.38% x̄: 12.96% x̃: 11.94%
95% mean confidence interval for sstall value: 1.83 4.62
95% mean confidence interval for sstall %-change: 6.60% 11.48%
Sstall are HURT.
total (ss) in shared programs: 67114 -> 67408 (0.44%)
(ss) in affected programs: 2292 -> 2586 (12.83%)
helped: 19
HURT: 57
helped stats (abs) min: 1 max: 2 x̄: 1.05 x̃: 1
helped stats (rel) min: 2.08% max: 33.33% x̄: 8.81% x̃: 7.14%
HURT stats (abs) min: 1 max: 63 x̄: 5.51 x̃: 3
HURT stats (rel) min: 0.00% max: 55.00% x̄: 18.54% x̃: 18.18%
95% mean confidence interval for (ss) value: 1.99 5.75
95% mean confidence interval for (ss) %-change: 8.02% 15.38%
(ss) are HURT.
total systall in shared programs: 718495 -> 718907 (0.06%)
systall in affected programs: 14011 -> 14423 (2.94%)
helped: 43
HURT: 114
helped stats (abs) min: 1 max: 29 x̄: 4.79 x̃: 2
helped stats (rel) min: 0.30% max: 100.00% x̄: 7.55% x̃: 2.78%
HURT stats (abs) min: 1 max: 56 x̄: 5.42 x̃: 3
HURT stats (rel) min: 0.00% max: 700.00% x̄: 17.86% x̃: 2.90%
95% mean confidence interval for systall value: 1.27 3.97
95% mean confidence interval for systall %-change: 1.05% 20.75%
Systall are HURT.
total (sy) in shared programs: 22961 -> 23226 (1.15%)
(sy) in affected programs: 738 -> 1003 (35.91%)
helped: 4
HURT: 42
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 14.29% max: 50.00% x̄: 32.14% x̃: 32.14%
HURT stats (abs) min: 1 max: 63 x̄: 6.40 x̃: 4
HURT stats (rel) min: 6.67% max: 100.00% x̄: 35.84% x̃: 36.67%
95% mean confidence interval for (sy) value: 2.83 8.69
95% mean confidence interval for (sy) %-change: 21.76% 38.10%
(sy) are HURT.
total waves in shared programs: 556366 -> 556370 (<.01%)
waves in affected programs: 54 -> 58 (7.41%)
helped: 6
HURT: 2
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 25.00% max: 100.00% x̄: 50.00% x̃: 50.00%
HURT stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
95% mean confidence interval for waves value: -1.82 2.82
95% mean confidence interval for waves %-change: -8.44% 66.78%
Inconclusive result (value mean confidence interval includes 0).
total loops in shared programs: 456 -> 456 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
</pre>
</details>
<details>
<summary>a660 shader-db including Rob's shaders</summary>
<pre>
total instructions in shared programs: 4188898 -> 4145010 (-1.05%)
instructions in affected programs: 1379336 -> 1335448 (-3.18%)
helped: 1776
HURT: 82
helped stats (abs) min: 1 max: 652 x̄: 24.96 x̃: 8
helped stats (rel) min: 0.04% max: 29.15% x̄: 4.29% x̃: 2.94%
HURT stats (abs) min: 1 max: 46 x̄: 5.45 x̃: 2
HURT stats (rel) min: 0.06% max: 8.22% x̄: 1.30% x̃: 0.64%
95% mean confidence interval for instructions value: -25.81 -21.43
95% mean confidence interval for instructions %-change: -4.26% -3.83%
Instructions are helped.
total nops in shared programs: 947986 -> 914913 (-3.49%)
nops in affected programs: 483546 -> 450473 (-6.84%)
helped: 1712
HURT: 131
helped stats (abs) min: 1 max: 488 x̄: 19.73 x̃: 6
helped stats (rel) min: 0.18% max: 66.67% x̄: 9.84% x̃: 8.92%
HURT stats (abs) min: 1 max: 58 x̄: 5.40 x̃: 2
HURT stats (rel) min: 0.27% max: 41.23% x̄: 6.99% x̃: 3.60%
95% mean confidence interval for nops value: -19.62 -16.27
95% mean confidence interval for nops %-change: -9.06% -8.22%
Nops are helped.
total non-nops in shared programs: 3240912 -> 3230097 (-0.33%)
non-nops in affected programs: 882671 -> 871856 (-1.23%)
helped: 1783
HURT: 19
helped stats (abs) min: 1 max: 164 x̄: 6.13 x̃: 2
helped stats (rel) min: 0.09% max: 16.23% x̄: 1.87% x̃: 0.83%
HURT stats (abs) min: 1 max: 54 x̄: 6.42 x̃: 2
HURT stats (rel) min: 0.17% max: 5.65% x̄: 0.88% x̃: 0.42%
95% mean confidence interval for non-nops value: -6.57 -5.43
95% mean confidence interval for non-nops %-change: -1.97% -1.72%
Non-nops are helped.
total mov in shared programs: 157785 -> 157648 (-0.09%)
mov in affected programs: 22512 -> 22375 (-0.61%)
helped: 146
HURT: 107
helped stats (abs) min: 1 max: 21 x̄: 4.23 x̃: 3
helped stats (rel) min: 0.35% max: 100.00% x̄: 13.82% x̃: 8.70%
HURT stats (abs) min: 1 max: 73 x̄: 4.49 x̃: 2
HURT stats (rel) min: 0.37% max: 150.00% x̄: 13.05% x̃: 8.00%
95% mean confidence interval for mov value: -1.43 0.35
95% mean confidence interval for mov %-change: -5.19% 0.29%
Inconclusive result (value mean confidence interval includes 0).
total cov in shared programs: 87321 -> 87300 (-0.02%)
cov in affected programs: 62 -> 41 (-33.87%)
helped: 6
HURT: 0
helped stats (abs) min: 1 max: 16 x̄: 3.50 x̃: 1
helped stats (rel) min: 3.85% max: 94.12% x̄: 32.60% x̃: 25.00%
95% mean confidence interval for cov value: -9.93 2.93
95% mean confidence interval for cov %-change: -66.45% 1.25%
Inconclusive result (value mean confidence interval includes 0).
total dwords in shared programs: 8822092 -> 8800964 (-0.24%)
dwords in affected programs: 1494868 -> 1473740 (-1.41%)
helped: 813
HURT: 28
helped stats (abs) min: 2 max: 352 x̄: 26.39 x̃: 24
helped stats (rel) min: 0.04% max: 25.00% x̄: 2.88% x̃: 1.52%
HURT stats (abs) min: 2 max: 96 x̄: 11.64 x̃: 4
HURT stats (rel) min: 0.07% max: 3.42% x̄: 0.79% x̃: 0.40%
95% mean confidence interval for dwords value: -27.43 -22.82
95% mean confidence interval for dwords %-change: -3.03% -2.49%
Dwords are helped.
total last-baryf in shared programs: 138874 -> 138990 (0.08%)
last-baryf in affected programs: 1278 -> 1394 (9.08%)
helped: 18
HURT: 19
helped stats (abs) min: 1 max: 13 x̄: 4.39 x̃: 3
helped stats (rel) min: 2.78% max: 72.22% x̄: 15.83% x̃: 9.64%
HURT stats (abs) min: 2 max: 31 x̄: 10.26 x̃: 11
HURT stats (rel) min: 4.11% max: 260.00% x̄: 95.25% x̃: 22.86%
95% mean confidence interval for last-baryf value: 0.00 6.27
95% mean confidence interval for last-baryf %-change: 8.78% 73.64%
Last-baryf are HURT.
total last-helper in shared programs: 1143827 -> 1126798 (-1.49%)
last-helper in affected programs: 578828 -> 561799 (-2.94%)
helped: 678
HURT: 108
helped stats (abs) min: 1 max: 465 x̄: 27.74 x̃: 15
helped stats (rel) min: 0.15% max: 67.48% x̄: 6.75% x̃: 3.60%
HURT stats (abs) min: 1 max: 139 x̄: 16.45 x̃: 6
HURT stats (rel) min: 0.07% max: 104.76% x̄: 8.98% x̃: 1.97%
95% mean confidence interval for last-helper value: -24.58 -18.75
95% mean confidence interval for last-helper %-change: -5.41% -3.76%
Last-helper are helped.
total half in shared programs: 0 -> 0
half in affected programs: 0 -> 0
helped: 0
HURT: 0
total full in shared programs: 224530 -> 224480 (-0.02%)
full in affected programs: 390 -> 340 (-12.82%)
helped: 36
HURT: 10
helped stats (abs) min: 1 max: 16 x̄: 2.22 x̃: 2
helped stats (rel) min: 12.50% max: 37.50% x̄: 23.66% x̃: 25.00%
HURT stats (abs) min: 1 max: 6 x̄: 3.00 x̃: 2
HURT stats (rel) min: 25.00% max: 60.00% x̄: 35.50% x̃: 25.00%
95% mean confidence interval for full value: -2.07 -0.10
95% mean confidence interval for full %-change: -18.62% -2.98%
Full are helped.
total constlen in shared programs: 609804 -> 609804 (0.00%)
constlen in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat0 in shared programs: 1041898 -> 1008830 (-3.17%)
cat0 in affected programs: 523961 -> 490893 (-6.31%)
helped: 1712
HURT: 131
helped stats (abs) min: 1 max: 488 x̄: 19.73 x̃: 6
helped stats (rel) min: 0.17% max: 50.00% x̄: 8.99% x̃: 8.22%
HURT stats (abs) min: 1 max: 58 x̄: 5.39 x̃: 2
HURT stats (rel) min: 0.25% max: 37.90% x̄: 6.20% x̃: 3.26%
95% mean confidence interval for cat0 value: -19.61 -16.27
95% mean confidence interval for cat0 %-change: -8.28% -7.54%
Cat0 are helped.
total cat1 in shared programs: 246616 -> 246468 (-0.06%)
cat1 in affected programs: 35242 -> 35094 (-0.42%)
helped: 150
HURT: 106
helped stats (abs) min: 1 max: 20 x̄: 4.17 x̃: 3
helped stats (rel) min: 0.25% max: 100.00% x̄: 8.70% x̃: 5.21%
HURT stats (abs) min: 1 max: 73 x̄: 4.50 x̃: 2
HURT stats (rel) min: 0.26% max: 150.00% x̄: 8.33% x̃: 3.12%
95% mean confidence interval for cat1 value: -1.47 0.32
95% mean confidence interval for cat1 %-change: -3.88% 0.57%
Inconclusive result (value mean confidence interval includes 0).
total cat2 in shared programs: 1516785 -> 1506113 (-0.70%)
cat2 in affected programs: 437420 -> 426748 (-2.44%)
helped: 1798
HURT: 0
helped stats (abs) min: 1 max: 160 x̄: 5.94 x̃: 2
helped stats (rel) min: 0.28% max: 32.05% x̄: 3.71% x̃: 1.58%
95% mean confidence interval for cat2 value: -6.49 -5.38
95% mean confidence interval for cat2 %-change: -3.96% -3.46%
Cat2 are helped.
total cat3 in shared programs: 1195536 -> 1195536 (0.00%)
cat3 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat4 in shared programs: 84057 -> 84057 (0.00%)
cat4 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat5 in shared programs: 47537 -> 47537 (0.00%)
cat5 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat6 in shared programs: 53323 -> 53323 (0.00%)
cat6 in affected programs: 0 -> 0
helped: 0
HURT: 0
total cat7 in shared programs: 3146 -> 3146 (0.00%)
cat7 in affected programs: 0 -> 0
helped: 0
HURT: 0
total stp in shared programs: 2452 -> 2452 (0.00%)
stp in affected programs: 0 -> 0
helped: 0
HURT: 0
total ldp in shared programs: 572 -> 572 (0.00%)
ldp in affected programs: 0 -> 0
helped: 0
HURT: 0
total sstall in shared programs: 363810 -> 364867 (0.29%)
sstall in affected programs: 74696 -> 75753 (1.42%)
helped: 190
HURT: 381
helped stats (abs) min: 1 max: 67 x̄: 7.26 x̃: 5
helped stats (rel) min: 0.16% max: 100.00% x̄: 15.27% x̃: 7.75%
HURT stats (abs) min: 1 max: 118 x̄: 6.40 x̃: 3
HURT stats (rel) min: 0.00% max: 700.00% x̄: 22.22% x̃: 7.84%
95% mean confidence interval for sstall value: 0.99 2.71
95% mean confidence interval for sstall %-change: 5.37% 14.11%
Sstall are HURT.
total (ss) in shared programs: 90388 -> 91478 (1.21%)
(ss) in affected programs: 21370 -> 22460 (5.10%)
helped: 168
HURT: 282
helped stats (abs) min: 1 max: 11 x̄: 2.55 x̃: 1
helped stats (rel) min: 1.01% max: 100.00% x̄: 12.30% x̃: 7.69%
HURT stats (abs) min: 1 max: 81 x̄: 5.38 x̃: 2
HURT stats (rel) min: 1.14% max: 200.00% x̄: 17.84% x̃: 9.84%
95% mean confidence interval for (ss) value: 1.49 3.36
95% mean confidence interval for (ss) %-change: 3.85% 9.32%
(ss) are HURT.
total systall in shared programs: 783846 -> 784779 (0.12%)
systall in affected programs: 206410 -> 207343 (0.45%)
helped: 267
HURT: 211
helped stats (abs) min: 1 max: 157 x̄: 16.01 x̃: 5
helped stats (rel) min: 0.06% max: 92.00% x̄: 9.63% x̃: 4.17%
HURT stats (abs) min: 1 max: 311 x̄: 24.68 x̃: 8
HURT stats (rel) min: 0.00% max: 200.00% x̄: 12.71% x̃: 5.88%
95% mean confidence interval for systall value: -1.84 5.75
95% mean confidence interval for systall %-change: -1.66% 2.12%
Inconclusive result (value mean confidence interval includes 0).
total (sy) in shared programs: 38045 -> 39059 (2.67%)
(sy) in affected programs: 6354 -> 7368 (15.96%)
helped: 78
HURT: 147
helped stats (abs) min: 1 max: 6 x̄: 1.40 x̃: 1
helped stats (rel) min: 0.55% max: 50.00% x̄: 14.88% x̃: 13.39%
HURT stats (abs) min: 1 max: 81 x̄: 7.64 x̃: 3
HURT stats (rel) min: 0.28% max: 100.00% x̄: 26.32% x̃: 25.00%
95% mean confidence interval for (sy) value: 2.80 6.21
95% mean confidence interval for (sy) %-change: 8.75% 15.32%
(sy) are HURT.
total waves in shared programs: 606238 -> 606276 (<.01%)
waves in affected programs: 316 -> 354 (12.03%)
helped: 27
HURT: 10
helped stats (abs) min: 2 max: 4 x̄: 2.30 x̃: 2
helped stats (rel) min: 20.00% max: 50.00% x̄: 28.02% x̃: 25.00%
HURT stats (abs) min: 2 max: 4 x̄: 2.40 x̃: 2
HURT stats (rel) min: 25.00% max: 33.33% x̄: 27.50% x̃: 25.00%
95% mean confidence interval for waves value: 0.28 1.77
95% mean confidence interval for waves %-change: 4.40% 21.63%
Waves are helped.
total loops in shared programs: 1144 -> 1144 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
</pre>
</details>
<details>
<summary>a660 fossils including some private fossils</summary>
<pre>
Totals:
MaxWaves: 1525588 -> 1525922 (+0.02%); split: +0.03%, -0.01%
Instrs: 48395451 -> 47821017 (-1.19%); split: -1.28%, +0.09%
CodeSize: 95156426 -> 94827776 (-0.35%); split: -0.41%, +0.06%
NOPs: 9922033 -> 9497906 (-4.27%); split: -4.50%, +0.23%
MOVs: 3005535 -> 3004942 (-0.02%); split: -1.05%, +1.03%
Full: 1844552 -> 1843635 (-0.05%); split: -0.07%, +0.02%
(ss): 1253293 -> 1252074 (-0.10%); split: -0.95%, +0.85%
(sy): 529048 -> 532171 (+0.59%); split: -0.70%, +1.29%
(ss)-stall: 3579990 -> 3595255 (+0.43%); split: -0.92%, +1.35%
(sy)-stall: 14221917 -> 14240030 (+0.13%); split: -0.80%, +0.93%
STPs: 82093 -> 81899 (-0.24%)
LDPs: 121029 -> 120603 (-0.35%)
Subgroup size: 12046400 -> 12046464 (+0.00%)
Cat0: 10562989 -> 10139632 (-4.01%); split: -4.22%, +0.21%
Cat1: 4064817 -> 4053403 (-0.28%); split: -1.48%, +1.20%
Cat2: 17826021 -> 17686886 (-0.78%)
Cat6: 749632 -> 749104 (-0.07%)
Totals from 30438 (21.36% of 142514) affected shaders:
MaxWaves: 187396 -> 187730 (+0.18%); split: +0.22%, -0.04%
Instrs: 30736273 -> 30161839 (-1.87%); split: -2.01%, +0.14%
CodeSize: 54656008 -> 54327358 (-0.60%); split: -0.71%, +0.11%
NOPs: 7586476 -> 7162349 (-5.59%); split: -5.89%, +0.30%
MOVs: 1901025 -> 1900432 (-0.03%); split: -1.66%, +1.62%
Full: 655596 -> 654679 (-0.14%); split: -0.19%, +0.05%
(ss): 808975 -> 807756 (-0.15%); split: -1.47%, +1.32%
(sy): 340308 -> 343431 (+0.92%); split: -1.09%, +2.01%
(ss)-stall: 2658569 -> 2673834 (+0.57%); split: -1.24%, +1.81%
(sy)-stall: 8076078 -> 8094191 (+0.22%); split: -1.41%, +1.63%
STPs: 47870 -> 47676 (-0.41%)
LDPs: 84950 -> 84524 (-0.50%)
Subgroup size: 3182272 -> 3182336 (+0.00%)
Cat0: 8063124 -> 7639767 (-5.25%); split: -5.53%, +0.28%
Cat1: 2481615 -> 2470201 (-0.46%); split: -2.42%, +1.96%
Cat2: 11216283 -> 11077148 (-1.24%)
Cat6: 379784 -> 379256 (-0.14%)
</pre>
</details>
Note that the `(ss)`-stall and `(sy)`-stall stats are hurt in general. While I'd like to investigate this a bit further, I have two observations:
- Since the overall instruction count goes down, there are probably just less instructions available to fill stall cycles.
- I noticed some shaders where essentially nothing changed by this series but some stats are still hurt. This seems to be caused by slightly different scheduling decisions: before this series, once an instruction with a predicate destination would be scheduled in a block, subsequent ones would not get scheduled until there was no other choice left because of a predicate conflict. This restriction has now been removed which often causes subsequent predicate writes to be scheduled earlier. This seems to have a ripple effect that sometimes hurts certain stats.Job NoormanJob Noormanhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27266freedreno/crashdec: Initial a7xx support2024-01-25T13:37:00ZConnor Abbottfreedreno/crashdec: Initial a7xx supportThere are more things to do, e.g. BV mempool dumping and estimating the
BV location. However this is a good start.
The expanded register size is because the reglist includes registers
from other cores and these are read the same as any ...There are more things to do, e.g. BV mempool dumping and estimating the
BV location. However this is a good start.
The expanded register size is because the reglist includes registers
from other cores and these are read the same as any other GPU register.
Note that this is also the actual range of type4 packets, even though
registers higher than 0xffff are all protected. Right now these are
skipped on page faults but still read with the crashdumper for hangs.
The associated kernel series is at https://patchwork.freedesktop.org/series/129163/.Rob ClarkRob Clarkhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27123freedreno/replay: Use real queueid for submissions and waits2024-01-17T17:45:57ZDanylo Piliaievfreedreno/replay: Use real queueid for submissions and waits### What does this MR do and why?
Otherwise it failed when expected queueid is not 0.
---
I feel like I already should have fixed this but I cannot find any evidence that I fixed it earlier somewhere.### What does this MR do and why?
Otherwise it failed when expected queueid is not 0.
---
I feel like I already should have fixed this but I cannot find any evidence that I fixed it earlier somewhere.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26800nir: properly split CS sys vals into API and driver variants (_zero_base)2024-02-19T15:35:59ZKarol Herbstkherbst@redhat.comnir: properly split CS sys vals into API and driver variants (_zero_base)This always annoyed me, that drivers have to deal with both. Just make the "API" variants always lower to the `_zero_base` ones to make it easier on drivers. This also fixes range analysis trying to optimize the "API" sys vals with hardw...This always annoyed me, that drivers have to deal with both. Just make the "API" variants always lower to the `_zero_base` ones to make it easier on drivers. This also fixes range analysis trying to optimize the "API" sys vals with hardware limits, even though they are unbound in e.g. OpenCL.
I also don't like the `_zero_base` naming, but this can kept until we have a better name.
I think I've figured out all regressions, and hopefully this makes handling of compute sysvals more sane in the future.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26771freedreno/afuc: Support assembling firmwares on a660 and a7xx2024-02-02T17:29:13ZConnor Abbottfreedreno/afuc: Support assembling firmwares on a660 and a7xxThe main problem with assembling anything newer than `a650_sqe.fw` has been the multiple sections that need to be assembled and then concatenated together for BV and LPAC firmwares. This adds support for a `.section` directive and makes ...The main problem with assembling anything newer than `a650_sqe.fw` has been the multiple sections that need to be assembled and then concatenated together for BV and LPAC firmwares. This adds support for a `.section` directive and makes the disassembler output it. We also need more flexible jump table handling to support the case where there is data after the jump table or the jump table offset is not at dword 1. It turns out there were some bugs with assembling newer a7xx instructions because it wasn't tested, so this series also fixes those, and an extra modifier was missing which only turned up when reassembling didn't return the same bytes. Finally we add a testcase for testing the new a7xx instructions and section handling.
I've tested that `a660_sqe.fw`, `a730_sqe.fw`, and `a740_sqe.fw` now reassemble to an identical binary, although it looks like there is one unknown instruction on a7xx. Of course, for reassembling you need to add relocations, and I've added a section of the README describing that.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578turnip: VK_EXT_host_image_copy2024-02-27T12:06:08ZConnor Abbottturnip: VK_EXT_host_image_copyThis extension will be used to accelerate uploads and downloads of tiled images, especially block-compressed images, by avoiding an extra staging buffer and copy on the GPU. It is already used in zink, dxvk, and vkd3d-proton.
In order t...This extension will be used to accelerate uploads and downloads of tiled images, especially block-compressed images, by avoiding an extra staging buffer and copy on the GPU. It is already used in zink, dxvk, and vkd3d-proton.
In order to implement this we need an accelerated implementation of the Adreno tiling scheme. I've added the core tiling/untiling routines to fdl, inspired by `isl_tiled_memcpy.c`, and it could be useful for freedreno too. There is also documentation of the reverse-engineered scheme in a comment. Note that this doesn't implement UBWC compression/decompression, only tiling, as is expected for implementations of this extension.
I have vkoverhead patches to test the performance of `fd6_tiled_memcpy`. There is also a pending VK-GL-CTS CL to more thoroughly test this.
The tiling scheme depends on a parameter called the "highest bank bit" that is programmed into registers by the kernel. This means that we ideally should get the value from the kernel. This series includes a fallback which attempts to guess what value the kernel set, but there will be kernel and virgl-renderer patches to expose it to userspace, and we shouldn't land this MR without using that uABI to avoid accidentally making the value programmed by the kernel uABI. As long as we use the new uABI here, old mesa will not care about the highest bank bit whereas newer mesa will always get it from the kernel first, so it should be safe to change the value in the kernel if we need to (e.g. to fix the a650 bug).https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26203Replace dup() with os_dupfd_cloexec()2023-12-01T07:37:07ZSimon Sercontact@emersion.frReplace dup() with os_dupfd_cloexec()dup() will leak the new FD into any child process after fork().dup() will leak the new FD into any child process after fork().https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26154turnip: Implement missing partial depth/stencil binding2023-12-05T22:03:38ZConnor Abbottturnip: Implement missing partial depth/stencil bindingWe missed this when bringing up VK_KHR_dynamic_rendering. Fortunately there's a HW feature to make this possible without fiddling with depth/stencil state.We missed this when bringing up VK_KHR_dynamic_rendering. Fortunately there's a HW feature to make this possible without fiddling with depth/stencil state.Connor AbbottConnor Abbotthttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26015RFC: freedreno/ci: Skip some uselessly duplicated pipeline tests2024-01-18T11:34:19ZConnor AbbottRFC: freedreno/ci: Skip some uselessly duplicated pipeline testsThis is a strawman proposal with a list of shader object tests to skip in CI. Hopefully this should help mitigate the runtime increase.
I think that in the future we should also push to have these removed from VK-GL-CTS altogether, whic...This is a strawman proposal with a list of shader object tests to skip in CI. Hopefully this should help mitigate the runtime increase.
I think that in the future we should also push to have these removed from VK-GL-CTS altogether, which will also bring down the test setup cost, but that will take longer.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25916nir: I/O vector access improvements2023-11-15T02:53:46ZFaith Ekstrandnir: I/O vector access improvementsThis MR does two things:
1. On NVIDIA, we can indirect access anything, including within a vector and I'd like to avoid lowering to if-ladders if we can. The first 4 commits of this MR make it so that we can indirect on compact variable...This MR does two things:
1. On NVIDIA, we can indirect access anything, including within a vector and I'd like to avoid lowering to if-ladders if we can. The first 4 commits of this MR make it so that we can indirect on compact variables such as tess levels and clip/cull distances. The annoying bit is that this means changing the interface of the `type_size` callback to `nir_lower_io()` which involves touching a lot of drivers.
2. We also need to get SPIR-V doing the right thing on TCS outputs. Right now, if the SPIR-V has a write to a single component of a vector, `spirv_to_nir` emits a load/insert/store pattern which is potentially racy. On NVIDIA, there are CTS tests which actually hit this race so I need this for passing CTS. We have a NIR pass which lowers writes of this form to an if-ladder with write-masks which is what we use for most drivers.MR Label MakerMR Label Makerhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25872Draft: ci: Pull in VK CTS ESO test perf fix (and a couple others)2023-11-14T10:58:12ZEmma Anholtemma@anholt.netDraft: ci: Pull in VK CTS ESO test perf fix (and a couple others)hopefully with this we can get vk full runs working again.hopefully with this we can get vk full runs working again.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25838janitor: use fi and di from u_math.h across the tree2023-10-30T21:47:41ZFerdinand Bachmannjanitor: use fi and di from u_math.h across the treeThis MR addresses issue #9847.
This is mostly a relatively straightforward translation from various ad-hoc copies of `union fi` and `union di` to the common definition in `u_math.h`. This MR also removes the last remaining definition (`...This MR addresses issue #9847.
This is mostly a relatively straightforward translation from various ad-hoc copies of `union fi` and `union di` to the common definition in `u_math.h`. This MR also removes the last remaining definition (`fi_type`) from `mesa_private.h`, removing that header.
## Converted usage sites
- `src/util/`:
- `format_rgb9e5.h`: straightforward conversion from custom union to `fi`
- `format_r11g11b10f.h`: straightforward conversion from custom union to `fi`
- `format_srgb.h`: straightforward conversion from custom union to `fi`
- `bitpack_helpers.h`: straightforward conversion from custom union to `fi`
- `half_float.c`: straightforward conversion from custom union to `fi`
- `softfloat.c`: straightforward conversion from custom unions to `fi` and `di`
- `src/intel/isl`:
- `isl_emit_depth_stencil.c`: straightforward conversion from custom union to `fi`
- `src/freedreno/rnn`:
- `rnndec.c`: partially converted; converted use in `float float16(uint16_t)`
- `src/gallium/drivers/nouveau`:
- `nouveau_winsys.h`: straightforward conversion from custom union to `fi`
- `src/gallium/frontends/nine`:
- `nine_helpers.h`: straightforward conversion from custom union to `fi`
- `src/mesa/main`:
- `mesa_private.h`: previously defined `fi_type`, now everything that used that now uses `union fi`
the file became empty by removing that definition, so I removed the file
- `macros.h`: some macros required changing to adjust to the different member names of `union fi`
- `context.c`: adjust member name `.u` to `.ui`
- `tests/disable_windows_include.c`: remove `mesa_private.h`
- `src/mesa/vbo`:
- `vbo.h`: switch from `fi_type` to `union fi`
- `vbo_save.h`: switch from `fi_type` to `union fi`
- `vbo_private.h` switch from `fi_type` to `union fi`
- `vbo_exec.c`, `vbo_exec_api.c`, `vbo_exec_draw.c`: switch from `fi_type` to `union fi`
- `vbo_save_api.c`, `vbo_save_draw.c`, `vbo_save_loopback.c`: switch form `fi_type` to `union fi`
## Skipped usage sites
- `src/intel/vulkan/grl`:
- `include/GRLOCLCompatibility.h`: unsure if this should use `fi`
since the header seems to go out of its way not to depend on other mesa things
- `src/freedreno/rnn`:
- `rnndec.c`: partially converted; skipped use in `rnndec_decodeval`
since it uses the same union to pun between `uint64_t`, `float`, and `double`
while `fi` and `di` only support either punning to `float` or `double`
- `src/imgui`:
- `imgui.h`: external library vendored into mesa
also uses the same union to pun between more types: `int`, `float`, `void*`
This PR is no longer a draft, but I'm still combing through the tree and adding commits as I find instances of this.
I will squash the individual commits into one big janitor commit before this is merged, but leave it separated while I'm working on it to keep track of what I have already done.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25454tu: Support AHardwareBuffer2024-02-22T08:23:19Ztarsintu: Support AHardwareBufferDepends on: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25360 !25455 !25410
Tested with u_gralloc IMapper4 API on Android 13
https://gitlab.freedesktop.org/mesa/mesa/-/issues/9691 https://gitlab.freedesktop.org/mesa/mesa...Depends on: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25360 !25455 !25410
Tested with u_gralloc IMapper4 API on Android 13
https://gitlab.freedesktop.org/mesa/mesa/-/issues/9691 https://gitlab.freedesktop.org/mesa/mesa/-/issues/9874