mesa merge requestshttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests2023-02-07T17:59:37Zhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21093anv: prep work for execbuffer32023-02-07T17:59:37ZPaulo Zanonianv: prep work for execbuffer3Here are some changes that are part of !21057 and have some value on their own and could be merged before the rest, at least IMHO. This rework makes the anv_execbuf layer a little more execbuffer-version-agnostic, pushing the execbuffer-...Here are some changes that are part of !21057 and have some value on their own and could be merged before the rest, at least IMHO. This rework makes the anv_execbuf layer a little more execbuffer-version-agnostic, pushing the execbuffer-version-dependent code to anv_gem_execbuffer(). The last patch changes how execbuf->objects is handled and may be a little more controversial, although I see it as a win.Paulo ZanoniPaulo Zanonihttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21057Draft: vm_bind/execbuffer3 implementation for Iris and Anv2023-10-23T11:04:49ZPaulo ZanoniDraft: vm_bind/execbuffer3 implementation for Iris and AnvThe vm_bind feature has many utilities, including reducing CPU overhead and allowing the implementation of Vulkan Sparse bindings, which will enable more DirectX 12 games to work.
The Kernel team is working on an implementation for it, ...The vm_bind feature has many utilities, including reducing CPU overhead and allowing the implementation of Vulkan Sparse bindings, which will enable more DirectX 12 games to work.
The Kernel team is working on an implementation for it, with many iterations posted to their mailing list:
- https://cgit.freedesktop.org/drm/drm-tip/tree/Documentation/gpu/rfc/i915_vm_bind.rst
- https://lists.freedesktop.org/archives/intel-gfx/2023-January/316417.html
This branch contains the Mesa implementation to use that interface. We probably shouldn't merge this yet since the Kernel team didn't merge their bits either, but we could (maybe I'd just need to create a separate header for the new interface).
This branch is not "final" or 100% tested yet. We do have a few known bugs and there are also some known improvements we can do to the codebase, but it mostly works and its final version will probably look very similar to what it is now. So please feel free to comment on the design.
Every patch that comes before `WIP: drm-uapi/i915_drm.h: update the headers for vm_bind` is prep work and can be considered for merging right now.
Running this branch on a Kernel without vm_bind should work 100% regression-free.Paulo ZanoniPaulo Zanonihttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20164Add missing dependencies for X11 build2022-12-06T14:05:59Zjheaff1Add missing dependencies for X11 buildMeson would fail to build unless the required headers were installed on
the host system.Meson would fail to build unless the required headers were installed on
the host system.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19414enable legacy dithering in runtime and anv driver2024-02-26T17:42:11ZTapani Pällienable legacy dithering in runtime and anv driverWe limit dithering for cases where blending is not enabled.We limit dithering for cases where blending is not enabled.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19398Draft: anv, iris changes for i915 adding gtt_alignment region info2023-03-16T20:29:06ZJordan JustenDraft: anv, iris changes for i915 adding gtt_alignment region infoI tested with intel/CI_DRM_12285. Crucible had no regressions with 64k gtt_alignment.
piglit's gpu profile got similar results with 64k and 2M alignment. (~120 fails, 4 crashes, ~26.2k passes)
Cc: @llandwerlin, @mwaI tested with intel/CI_DRM_12285. Crucible had no regressions with 64k gtt_alignment.
piglit's gpu profile got similar results with 64k and 2M alignment. (~120 fails, 4 crashes, ~26.2k passes)
Cc: @llandwerlin, @mwahttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17896anv: Add workaround for unsuccessful aux surface2022-11-29T23:22:41ZViktoriia Palianytsiaanv: Add workaround for unsuccessful aux surfaceIn the game Steel Rats we can find misrendering
issue that is caused by creating unsuccessful
aux surface.
~~If we return VK_SUCCESS from
the function add_aux_surface_if_supported in
anv_image.c, then the process of creating
VkImage stop...In the game Steel Rats we can find misrendering
issue that is caused by creating unsuccessful
aux surface.
~~If we return VK_SUCCESS from
the function add_aux_surface_if_supported in
anv_image.c, then the process of creating
VkImage stops and bug is fixed.~~
**Updated:**
After longer investigation workaround was changed and placed in `add_all_surfaces_implicit_layout` function with purpose to skip process of creation auxiliary surface. I have come to this decision because after looking over all functions that surface creation goes through nothing that can make bad changes to it and cause misrendering was not found. Also debugging flags that fix problem(those are nofc and norbc) just stop process of creating surface so the same does workaround but at earlier stage so in that way fix will be more optimized.
Closes: mesa/mesa#5807
Signed-off-by: Viktoriia Palianytsia <v.palianytsia@globallogic.com>https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17892Draft: anv: VK_EXT_attachment_feedback_loop_layout2023-06-08T12:57:13ZFaith EkstrandDraft: anv: VK_EXT_attachment_feedback_loop_layoutThere are also a bunch of core Vulkan changes to switch the common dynamic rendering code over to it as well.There are also a bunch of core Vulkan changes to switch the common dynamic rendering code over to it as well.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17161anv: Use sampleLocationsEnable for sample locations2022-07-28T10:01:33ZMichael Skorokhodovwine@samsuper.xyzanv: Use sampleLocationsEnable for sample locationsAdding this to stable was requested by @mslusarz [here](https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17134#note_1436839).
Also, resolved merge conflict with commit 27ee40f4c9d86ed9190a8fee6d230e7416b288e3Adding this to stable was requested by @mslusarz [here](https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17134#note_1436839).
Also, resolved merge conflict with commit 27ee40f4c9d86ed9190a8fee6d230e7416b288e3https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16450WIP: nir: new lower divergent barriers pass2022-09-21T21:03:55ZLionel LandwerlinWIP: nir: new lower divergent barriers passUp to platforms like DG2, having workgroup barriers in divergent code
paths didn't really matter. But on DG2, the HW state machine will just
hang if a barrier is not reached by all lanes.
This pass works around this problem by splitting...Up to platforms like DG2, having workgroup barriers in divergent code
paths didn't really matter. But on DG2, the HW state machine will just
hang if a barrier is not reached by all lanes.
This pass works around this problem by splitting the shader into a
sequence on continuations executed within a loop in the main function
of the shader. The loop exits when all lanes have reach the end
continuation.
It reuses the excellent work done by @jekstrand in lower_shader_calls().https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16332Draft: anv: new cache infrastructure2023-07-04T09:48:20ZLionel LandwerlinDraft: anv: new cache infrastructureA while ago @fjdegroo noticed we did some pretty dumb stuff with regards to cache flushes.
Our current code looks at source & destination of barriers in isolation. So it can't tell whether a barrier moves things to/from the same HW unit...A while ago @fjdegroo noticed we did some pretty dumb stuff with regards to cache flushes.
Our current code looks at source & destination of barriers in isolation. So it can't tell whether a barrier moves things to/from the same HW unit for instance. In which case we could just optimize the barrier away.
We can do a lot better though. If you have a map of cache structure, you can find the fastest path from/to HW units and avoid going to main memory. This is what this MR implements.
CI run for this : https://mesa-ci.01.org/djdeath_vulkan/builds/1083/group/63a9f0ea7bb98050796b649e85481845https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16293intel: Asynchronous MI_LOAD_REGISTER_MEM for small performance gains2022-05-09T12:14:29ZKenneth Graunkekenneth@whitecape.orgintel: Asynchronous MI_LOAD_REGISTER_MEM for small performance gainsMI_LOAD_REGISTER_MEM has an "Async Mode Enable" bit which can be used to optimize back-to-back register writes. Normally, the command streamer waits to proceed to the next command until the value is fully committed to the MMIO register....MI_LOAD_REGISTER_MEM has an "Async Mode Enable" bit which can be used to optimize back-to-back register writes. Normally, the command streamer waits to proceed to the next command until the value is fully committed to the MMIO register. But when performing multiple writes in a row, we only need it to wait on the last write.
Such sections are common when dispatching indirect draws. As a prototype, I hacked iris to use indirect draws for every single non-BLORP draw call, and observed a 16% performance drop on Carchase (as a random app that's easy to run). This series improved performance by about 2% (so it was only 14.3% worse than direct draws). We'll obviously need to do other things to speed up indirect draws (Lionel has been prototyping some things), but this simple change at least gives us something for now.
Plus, this optimizes 64-bit register writes, which always involve two back-to-back MI_LOAD_REGISTER_MEM, since those only do 32 bits at a time.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15931Draft: iris: Implement clear_buffer with BLORP2022-07-06T09:15:14ZFaith EkstrandDraft: iris: Implement clear_buffer with BLORPThis is required currently by both clover and rusticlThis is required currently by both clover and rusticlhttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15138anv: fix get_tiling fail on gen122022-02-24T09:50:18ZXiaohui Guanv: fix get_tiling fail on gen12The problem is that nv_gem_get_tiling function
of uAPI will assert if the get/set tiling
is not supported. To fix this issue,
return directly in the function
anv_gem_get_tiling() if we don't
support get/set_tiling.
Signed-off-by: Junhao...The problem is that nv_gem_get_tiling function
of uAPI will assert if the get/set tiling
is not supported. To fix this issue,
return directly in the function
anv_gem_get_tiling() if we don't
support get/set_tiling.
Signed-off-by: Junhao Xin <junhao.xin@intel.com>https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15137anv: fix buf map failure in 32bits app2022-03-30T12:52:05ZXiaohui Guanv: fix buf map failure in 32bits appUse map64 instead of map for 32-bit applications
in anv_gem_mmap_offset to fix map failure.
Signed-off-by: Junhao Xin <junhao.xin@intel.com>Use map64 instead of map for 32-bit applications
in anv_gem_mmap_offset to fix map failure.
Signed-off-by: Junhao Xin <junhao.xin@intel.com>https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15015nir: Add and use glsl_get_shared_size_align_bytes()2022-03-01T22:58:04ZCaio Oliveiranir: Add and use glsl_get_shared_size_align_bytes()We use the same layout in many places, so let's add a function for it.We use the same layout in many places, so let's add a function for it.https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14432Draft: anv: Update the flushes emitted before PIPELINE_SELECT for TGL+2022-01-07T20:21:50ZCaio OliveiraDraft: anv: Update the flushes emitted before PIPELINE_SELECT for TGL+On top of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14301On top of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14301https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13294anv: fixup timestamp writes stage synchronization2022-03-15T20:19:50ZLionel Landwerlinanv: fixup timestamp writes stage synchronizationThe spec currently contradicts itself by forbidding and allowing
VK_PIPELINE_STAGE_2_NONE_KHR. This is about to be fixed. We also have
that new macro of the pipelined stages so we can use that.
Signed-off-by: Lionel Landwerlin <lionel.g...The spec currently contradicts itself by forbidding and allowing
VK_PIPELINE_STAGE_2_NONE_KHR. This is about to be fixed. We also have
that new macro of the pipelined stages so we can use that.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b996fa8efaa425 ("anv: implement VK_KHR_synchronization2")https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13274Draft: anv: build annotation buffers with INTEL_DEBUG=bat2022-12-30T11:57:23ZLionel LandwerlinDraft: anv: build annotation buffers with INTEL_DEBUG=batEssentially side buffer containing pointers to the batch and describing what it does.
End result (scrubbed a bit) :
```
0xfffffffeffffbf04: 0x7a000004: PIPE_CONTROL
...
DESC ANNOTATION: previous pc emitted=(+pb_stall +cs...Essentially side buffer containing pointers to the batch and describing what it does.
End result (scrubbed a bit) :
```
0xfffffffeffffbf04: 0x7a000004: PIPE_CONTROL
...
DESC ANNOTATION: previous pc emitted=(+pb_stall +cs_stall ) reason: gfx12_cmd_buffer_apply_pipe_flushes
0xfffffffeffffbf1c: 0x7b000005: 3DPRIMITIVE
...
0xfffffffeffffbf38: 0x10000002: MI_STORE_DATA_IMM
...
DESC ANNOTATION: pc queue=(+rt_flush +pb_stall ) reason: before blorp BTI change
0xfffffffeffffbf48: 0x7a000004: PIPE_CONTROL
...
DESC ANNOTATION: previous pc emitted=(+rt_flush +pb_stall +cs_stall ) reason: gfx12_cmd_buffer_apply_pipe_flushes
...
0xfffffffeffffc290: 0x7b000005: 3DPRIMITIVE
...
DESC ANNOTATION: pc queue=(+depth_flush +dc_flush +hdc_flush +rt_flush +tile_flush ) reason: pipe barrier
0xfffffffeffffc2ac: 0x7a000204: PIPE_CONTROL
...
DESC ANNOTATION: previous pc emitted=(+depth_flush +dc_flush +hdc_flush +rt_flush +tile_flush +pb_stall +depth_stall +cs_stall ) reason: gfx12_cmd_buffer_apply_pipe_flushes
```
Original idea by @ickle
~~What I haven't done is adding support for aubinator_error_decode yet, but that's easy.~~ **Done.**https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13242anv: implement split barriers for events2021-10-07T08:33:42ZLionel Landwerlinanv: implement split barriers for eventsWith the changes of the Vulkan API we can now implement event barriers
in 2 parts. The SetEvent API flushes and signals, the WaitEvent waits
and invalidates.
v2: Fix missing image memory barrier srcAccessMask
Signed-off-by: Lionel Land...With the changes of the Vulkan API we can now implement event barriers
in 2 parts. The SetEvent API flushes and signals, the WaitEvent waits
and invalidates.
v2: Fix missing image memory barrier srcAccessMask
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13162anv, crocus, iris: Try unsynchronized userptr if regular one fails2021-10-06T20:18:04ZEleni Maria Steaanv, crocus, iris: Try unsynchronized userptr if regular one failsThis patch is Jan Beich's downstream workaround for crocus, iris, and
anv to work well with Gen < 7. It is required to run Vulkan apps on FreeBSD on Gen < 7.<br/>
Link:<br/>
https://github.com/freebsd/freebsd-ports/blob/main/graphics/mes...This patch is Jan Beich's downstream workaround for crocus, iris, and
anv to work well with Gen < 7. It is required to run Vulkan apps on FreeBSD on Gen < 7.<br/>
Link:<br/>
https://github.com/freebsd/freebsd-ports/blob/main/graphics/mesa-devel/files/patch-userptr
Authored-by: Jan Beich <jbeich@freebsd.org><br/>
Reviewed-by: Eleni Maria Stea <elene.mst@gmail.com>
cc: @jbeich