freedreno: GL_PRIMITIVES_GENERATED doesn't count primitives when no one writes to gl_Position
Therefore freedreno fails the following tests:
glsl-1.50-geometry-primitive-types
glsl-1.50-geometry-primitive-id-restart
(Writing gl_Position
makes them pass)
Both of them don't write gl_Position
in VS/GS, don't have FS and both check a result of transform feedback based on GL_PRIMITIVES_GENERATED
query.
GL_PRIMITIVES_GENERATED
does read from RBBM_PRIMCTR_8
which is ras_primitives_in (how much primitives rasterizer received?), which is 0 when gl_Position
is undefined. However the RBBM_PRIMCTR_7
(gs_primitives_out) has a correct value in such case.
Blob work correctly, also it does more fancy things with counter regs:
Excerpt from blob (click me)
t7 opcode: CP_REG_TO_MEM (3e) (4 dwords)
{ REG = 0x432 | CNT = 2 | 64B }
{ DEST = 0xfd008 }
{ DEST_HI = 0x5 }
base register: RBBM_PERFCTR_PC_7_LO
gpuaddr:00000005000fd008
00000005000fd008: 0000: 03ce7fee
0000000500110280: 0000: 703e8003 40080432 000fd008 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE | WAIT_FOR_MEM_WRITES }
0000000500110290: 0000: 70738009 60000004 000fd010 00000005 000fd010 00000005 000fd008 00000005
00000005001102b0: 0020: 000fd000 00000005
t7 opcode: CP_COND_EXEC (44) (7 dwords)
{ ADDR0_LO = 0x82000 }
{ ADDR0_HI = 0x5 }
{ ADDR1_LO = 0x82008 }
{ ADDR1_HI = 0x5 }
{ REF = 0x1 }
{ DWORDS = 98 }
00000005001102b8: 0000: 70c48006 00082000 00000005 00082008 00000005 00000001 00000062
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
00000005001102d4: 0000: 70268000
t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = STOP_PRIMITIVE_CTRS }
event STOP_PRIMITIVE_CTRS
00000005001102d8: 0000: 70460001 0000000c
t7 opcode: CP_WAIT_MEM_WRITES (12) (1 dwords)
00000005001102e0: 0000: 70928000
t7 opcode: CP_REG_TO_MEM (3e) (4 dwords)
{ REG = 0x540 | CNT = 18 | 64B }
{ DEST = 0xf9060 }
{ DEST_HI = 0x5 }
base register: RBBM_PRIMCTR_0_LO
gpuaddr:00000005000f9060
00000005000f9060: 0000: 00000120 01000010 200200d0 00000100 001a0330 1000c901 11052050 500020d0
*
00000005001102e4: 0000: 703e8003 40480540 000f9060 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE | WAIT_FOR_MEM_WRITES }
00000005001102f4: 0000: 70738009 60000004 000f90c0 00000005 000f90c0 00000005 000f9060 00000005
0000000500110314: 0020: 000f9000 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
000000050011031c: 0000: 70738009 20000004 000f90c8 00000005 000f90c8 00000005 000f9068 00000005
000000050011033c: 0020: 000f9008 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
0000000500110344: 0000: 70738009 20000004 000f90d0 00000005 000f90d0 00000005 000f9070 00000005
0000000500110364: 0020: 000f9010 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
000000050011036c: 0000: 70738009 20000004 000f90d8 00000005 000f90d8 00000005 000f9078 00000005
000000050011038c: 0020: 000f9018 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
0000000500110394: 0000: 70738009 20000004 000f90e0 00000005 000f90e0 00000005 000f9080 00000005
00000005001103b4: 0020: 000f9020 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
00000005001103bc: 0000: 70738009 20000004 000f90e8 00000005 000f90e8 00000005 000f9088 00000005
00000005001103dc: 0020: 000f9028 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
00000005001103e4: 0000: 70738009 20000004 000f90f0 00000005 000f90f0 00000005 000f9090 00000005
0000000500110404: 0020: 000f9030 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
000000050011040c: 0000: 70738009 20000004 000f90f8 00000005 000f90f8 00000005 000f9098 00000005
000000050011042c: 0020: 000f9038 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
0000000500110434: 0000: 70738009 20000004 000f9100 00000005 000f9100 00000005 000f90a0 00000005
0000000500110454: 0020: 000f9040 00000005
t7 opcode: CP_COND_EXEC (44) (7 dwords)
{ ADDR0_LO = 0x82004 }
{ ADDR0_HI = 0x5 }
{ ADDR1_LO = 0x82008 }
{ ADDR1_HI = 0x5 }
{ REF = 0x1 }
{ DWORDS = 30 }
000000050011045c: 0000: 70c48006 00082004 00000005 00082008 00000005 00000001 0000001e
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000500110478: 0000: 70268000
t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = RST_VTX_CNT }
event RST_VTX_CNT
000000050011047c: 0000: 70460001 0000000e
t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = STAT_EVENT }
event STAT_EVENT
0000000500110484: 0000: 70460001 00000010
t7 opcode: CP_WAIT_MEM_WRITES (12) (1 dwords)
000000050011048c: 0000: 70928000
t7 opcode: CP_REG_TO_MEM (3e) (4 dwords)
{ REG = 0x552 | CNT = 4 | 64B }
{ DEST = 0xf90a8 }
{ DEST_HI = 0x5 }
base register: RBBM_PRIMCTR_9_LO
gpuaddr:00000005000f90a8
00000005000f90a8: 0000: 00000001 00104040
0000000500110490: 0000: 703e8003 40100552 000f90a8 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE | WAIT_FOR_MEM_WRITES }
00000005001104a0: 0000: 70738009 60000004 000f9108 00000005 000f9108 00000005 000f90a8 00000005
00000005001104c0: 0020: 000f9048 00000005
t7 opcode: CP_MEM_TO_MEM (73) (10 dwords)
{ NEG_C | DOUBLE }
00000005001104c8: 0000: 70738009 20000004 000f9110 00000005 000f9110 00000005 000f90b0 00000005
00000005001104e8: 0020: 000f9050 00000005
0000000500220248: 0000: 70bf8003 0011008c 00000005 00000119