offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
x5 = _BIT(x,5);
x5 = pipebit2 ^ y5;
tid_args[1] = ctx->i32_0;
tid_args[1] =
ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.lo", ctx->i32, tid_args, 2, AC_FUNC_ATTR_READNONE);
transform.coordOrigin = TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
transform.hasFixedUnit = !samplerUnitOut;
transform.fixedUnit = fixedUnit;
transform.base.prolog = pstip_transform_prolog;
transform.base.transform_declaration = pstip_transform_decl;
transform.base.transform_immediate = pstip_transform_immed;
tgsi_scan_shader(tokens, &transform.info);
transform.coordOrigin =
transform.info.properties[TGSI_PROPERTY_FS_COORD_ORIGIN];
if (i915->blitter &&
util_blitter_is_copy_supported(i915->blitter, resource, resource) &&
(usage & PIPE_MAP_WRITE) &&
!(usage & (PIPE_MAP_READ | PIPE_MAP_DONTBLOCK | PIPE_MAP_UNSYNCHRONIZED)))
use_staging_texture = TRUE;
use_staging_texture = FALSE;
surf.offset = dec->frame_size;
surf.width = 64;
surf.height = (templ->max_references + 1) * dec->frame_mbs / 4;
surf.depth = 1;
surf.base.format = PIPE_FORMAT_B8G8R8A8_UNORM;
surf.base.u.tex.level = 0;
surf.base.texture = &mip.base.base;
mip.level[0].tile_mode = 0;
mip.level[0].pitch = surf.width * 4;
mip.base.domain = NOUVEAU_BO_VRAM;
mip.base.bo = dec->mbring;
mip.base.address = dec->mbring->offset;
context->clear_render_target(context, &surf.base, &color, 0, 0, 64, 4760, false);
surf.offset = dec->vpring->size / 2 - 0x1000;
surf.width = 1024;
surf.height = 1;
mip.level[0].pitch = surf.width * 4;
mip.base.bo = dec->vpring;
mip.base.address = dec->vpring->offset;
context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1, false);
surf.offset = dec->vpring->size - 0x1000;
context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1, false);
surf->cb_color_view = color.view;
surf->cb_color_attrib = color.attrib;
surf->cb_color_fmask = color.fmask;
surf->cb_color_fmask_slice = color.fmask_slice;
surf->cb_color_view = 0;
output.type = 2;
output.op = CF_OP_EXPORT;
output.array_base = next_param++;
output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
enc->enc_pic.pc.enc_num_default_active_ref_l0 = 0x00000001;
enc->enc_pic.pc.enc_num_default_active_ref_l1 = 0x00000001;
enc->enc_pic.pc.enc_cabac_enable = pic->pic_ctrl.enc_cabac_enable;
enc->enc_pic.pc.enc_constraint_set_flags = pic->pic_ctrl.enc_constraint_set_flags;
enc->enc_pic.pc.enc_num_default_active_ref_l0 = 0x00000001;
enc->enc_pic.pc.enc_num_default_active_ref_l1 = 0x00000001;
enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask &
u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS);
enabled_shaderbuf = 0;
emit->tcs.inner.out_index = INVALID_INDEX;
emit->tcs.inner.out_index = INVALID_INDEX;
if (!job->msaa && info->src.resource->nr_samples > 1) {
job->msaa = true;
job->tile_width = 32;
job->tile_height = 32;
}
job->draw_min_x = info->dst.box.x;
job->draw_min_y = info->dst.box.y;
job->draw_max_x = info->dst.box.x + info->dst.box.width;
job->draw_max_y = info->dst.box.y + info->dst.box.height;
job->draw_width = dst_surf->width;
job->draw_height = dst_surf->height;
job->tile_width = tile_width;
job->tile_height = tile_height;
job->msaa = msaa;
last_inst != c->defs[src.index]) {
last_inst = qir_MOV_dest(c, qir_reg(QFILE_NULL, 0), src);
last_inst = (struct qinst *)c->cur_block->instructions.prev;
}
last_inst->sf = true;
pscreen->resource_destroy = u_resource_destroy_vtbl;
pscreen->resource_get_handle = vc4_resource_get_handle;
pscreen->resource_destroy = vc4_resource_destroy;
st->screen = pipe->screen;
st->pipe = pipe;
st->dirty = ST_ALL_STATES_MASK;
st->screen = screen;
aligned_y = y;
height_alignment = 2;
if (tiling == I915_TILING_X)
height_alignment = 8;
else if (tiling == I915_TILING_Y)
height_alignment = 32;
aligned_y = ALIGN(y, height_alignment);