[regression][bisected] dEQP-VK.spirv_assembly.{instruction,spirv1p4} test crashes on ANV
The following tests crash/segfault on ANV:
dEQP-VK.spirv_assembly.instruction.compute.ptr_access_chain.workgroup
dEQP-VK.spirv_assembly.instruction.compute.ptr_access_chain.workgroup_bad_stride
dEQP-VK.spirv_assembly.instruction.compute.ptr_access_chain.workgroup_no_stride
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrdiff.variable_pointers_vars_wg_diff
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrequal.variable_pointers_vars_wg_equal
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrequal.variable_pointers_wg_equal
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrnotequal.variable_pointers_vars_wg_not_equal
dEQP-VK.spirv_assembly.instruction.spirv1p4.opptrnotequal.variable_pointers_wg_not_equal
Bisected to:
commit 667e14e7bd759a77e732c4de09fb978ee3816eaf
Author: Karol Herbst <kherbst@redhat.com>
Date: Thu Mar 5 22:13:24 2020 +0100
nir/validate: validate the stride for deref_ptr_as_array
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4068>
Output from dEQP-VK.spirv_assembly.instruction.compute.ptr_access_chain.workgroup
on a gen9 GPU:
INTEL-MESA: debug: anv_GetPhysicalDeviceProperties2: ignored VkStructureType 1000237000
INTEL-MESA: error: ../src/intel/vulkan/anv_image.c:2190: VK_ERROR_OUT_OF_HOST_MEMORY
INTEL-MESA: error: ../src/intel/vulkan/genX_state.c:364: VK_ERROR_OUT_OF_HOST_MEMORY
NIR validation failed after spirv_to_nir
1 errors:
shader: MESA_SHADER_COMPUTE
local-size: 16, 1, 1
shared-size: 0
inputs: 0
outputs: 0
uniforms: 0
shared: 0
decl_var ssbo INTERP_MODE_NONE block @0 (~0, 0, 0)
decl_var ssbo INTERP_MODE_NONE block @1 (~0, 0, 1)
decl_var ssbo INTERP_MODE_NONE block @2 (~0, 0, 2)
decl_var shared INTERP_MODE_NONE uint[17] @3
decl_var system INTERP_MODE_NONE uvec3 @4
decl_function (null) (2 params)
impl (null) {
block block_0:
/* preds: */
vec1 32 ssa_0 = intrinsic load_param () (1) /* param_idx=1 */
vec1 32 ssa_1 = deref_cast (uint *)ssa_0 (shared uint) /* ptr_stride=0 */
vec1 32 ssa_2 = deref_cast (uint *)ssa_1 (shared uint) /* ptr_stride=0 */
vec1 32 ssa_3 = load_const (0x00000001 /* 0.000000 */)
vec1 32 ssa_4 = deref_ptr_as_array &(*ssa_2)[1] (shared uint) /* &(*(uint *)ssa_1)[1] */
error: nir_deref_instr_ptr_as_array_stride(parent) (../src/compiler/nir/nir_validate.c:485)
vec1 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */
vec1 32 ssa_6 = intrinsic load_param () (0) /* param_idx=0 */
vec1 32 ssa_7 = deref_cast (uint *)ssa_6 (function_temp uint) /* ptr_stride=0 */
intrinsic store_deref (ssa_7, ssa_5) (1, 0) /* wrmask=x */ /* access=0 */
return
/* succs: block_1 */
block block_1:
}
decl_function main (0 params)
impl main {
decl_var INTERP_MODE_NONE uint return_tmp
block block_0:
/* preds: */
vec1 32 ssa_29 = load_const (0x00000000 /* 0.000000 */)
vec1 32 ssa_24 = load_const (0x00000000 /* 0.000000 */)
vec1 32 ssa_0 = deref_var &@4 (system uvec3)
vec3 32 ssa_3 = intrinsic load_deref (ssa_0) (0) /* access=0 */
vec1 32 ssa_4 = mov ssa_3.x
vec1 32 ssa_5 = load_const (0x00000000 /* 0.000000 */)
vec1 64 ssa_6 = intrinsic vulkan_resource_index (ssa_5) (0, 0, 7) /* desc-set=0 */ /* binding=0 */ /* desc_type=SSBO */
vec1 64 ssa_7 = intrinsic load_vulkan_descriptor (ssa_6) (7) /* desc_type=SSBO */
vec1 64 ssa_8 = deref_cast (block *)ssa_7 (ssbo block) /* ptr_stride=0 */
vec1 64 ssa_9 = deref_struct &ssa_8->field0 (ssbo uint[]) /* &((block *)ssa_7)->field0 */
vec1 64 ssa_10 = i2i64 ssa_4
vec1 64 ssa_11 = deref_array &(*ssa_9)[ssa_10] (ssbo uint) /* &((block *)ssa_7)->field0[ssa_10] */
vec1 32 ssa_12 = intrinsic load_deref (ssa_11) (0) /* access=0 */
vec1 32 ssa_13 = load_const (0x00000000 /* 0.000000 */)
vec1 64 ssa_14 = intrinsic vulkan_resource_index (ssa_13) (0, 1, 7) /* desc-set=0 */ /* binding=1 */ /* desc_type=SSBO */
vec1 64 ssa_15 = intrinsic load_vulkan_descriptor (ssa_14) (7) /* desc_type=SSBO */
vec1 64 ssa_16 = deref_cast (block *)ssa_15 (ssbo block) /* ptr_stride=0 */
vec1 64 ssa_17 = deref_struct &ssa_16->field0 (ssbo uint[]) /* &((block *)ssa_15)->field0 */
vec1 64 ssa_18 = i2i64 ssa_4
vec1 64 ssa_19 = deref_array &(*ssa_17)[ssa_18] (ssbo uint) /* &((block *)ssa_15)->field0[ssa_18] */
vec1 32 ssa_20 = intrinsic load_deref (ssa_19) (0) /* access=0 */
vec1 32 ssa_21 = imul ssa_20, ssa_12
vec1 32 ssa_22 = deref_var &@3 (shared uint[17])
vec1 32 ssa_23 = deref_array &(*ssa_22)[ssa_4] (shared uint) /* &@3[ssa_4] */
intrinsic store_deref (ssa_23, ssa_21) (1, 0) /* wrmask=x */ /* access=0 */
vec1 1 ssa_25 = ieq ssa_4, ssa_24
/* succs: block_1 block_2 */
if ssa_25 {
block block_1:
/* preds: block_0 */
vec1 32 ssa_26 = deref_var &@3 (shared uint[17])
vec1 32 ssa_27 = load_const (0x00000010 /* 0.000000 */)
vec1 32 ssa_28 = deref_array &(*ssa_26)[16] (shared uint) /* &@3[16] */
intrinsic store_deref (ssa_28, ssa_29) (1, 0) /* wrmask=x */ /* access=0 */
/* succs: block_3 */
} else {
block block_2:
/* preds: block_0 */
/* succs: block_3 */
}
block block_3:
/* preds: block_1 block_2 */
intrinsic scoped_memory_barrier () (3, 944, 4) /* mem_semantics=ACQ|REL */ /* mem_modes=uniform|ubo|ssbo|shared|global */ /* mem_scope=DEVICE */
intrinsic control_barrier () ()
vec1 32 ssa_30 = deref_var &return_tmp (function_temp uint)
vec1 32 ssa_39 = deref_var &@3 (shared uint[17])
vec1 32 ssa_40 = deref_array &(*ssa_39)[ssa_4] (shared uint) /* &@3[ssa_4] */
call (null) ssa_30, ssa_40
vec1 32 ssa_31 = intrinsic load_deref (ssa_30) (0) /* access=0 */
vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */)
vec1 64 ssa_33 = intrinsic vulkan_resource_index (ssa_32) (0, 2, 7) /* desc-set=0 */ /* binding=2 */ /* desc_type=SSBO */
vec1 64 ssa_34 = intrinsic load_vulkan_descriptor (ssa_33) (7) /* desc_type=SSBO */
vec1 64 ssa_35 = deref_cast (block *)ssa_34 (ssbo block) /* ptr_stride=0 */
vec1 64 ssa_36 = deref_struct &ssa_35->field0 (ssbo uint[]) /* &((block *)ssa_34)->field0 */
vec1 64 ssa_37 = i2i64 ssa_4
vec1 64 ssa_38 = deref_array &(*ssa_36)[ssa_37] (ssbo uint) /* &((block *)ssa_34)->field0[ssa_37] */
intrinsic store_deref (ssa_38, ssa_31) (1, 0) /* wrmask=x */ /* access=0 */
return
/* succs: block_4 */
block block_4:
}