mesa issueshttps://gitlab.freedesktop.org/mesa/mesa/-/issues2024-02-13T07:21:54Zhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/10557r300: nine crash in r300_emit_vertex_arrays: Assertion `(buf)' failed.2024-02-13T07:21:54ZPavel Ondračkapavel.ondracka@gmail.comr300: nine crash in r300_emit_vertex_arrays: Assertion `(buf)' failed.`src/gallium/drivers/r300/r300_emit.c:972: r300_emit_vertex_arrays: Assertion `(buf)' failed.`
I've noticed this in the WIP CI nine testing branch https://gitlab.freedesktop.org/mesa/mesa/-/jobs/54609576, but I was not originally able t...`src/gallium/drivers/r300/r300_emit.c:972: r300_emit_vertex_arrays: Assertion `(buf)' failed.`
I've noticed this in the WIP CI nine testing branch https://gitlab.freedesktop.org/mesa/mesa/-/jobs/54609576, but I was not originally able to reproduce locally. Turns out this is due to use of uninitialized values, so sometimes the assertion in question is not hit (well at least on my ancient RV530 laptop with 32bit debian)
For example with `Xnine.fog` test:
```
==8299== Use of uninitialised value of size 4
==8299== at 0x56D4303: update_vertex_elements (nine_state.c:924)
==8299== by 0x56D7A92: nine_update_state (nine_state.c:1286)
==8299== by 0x56D93CD: nine_context_draw_indexed_primitive_from_vtxbuf_idxbuf_priv (nine_state.c:2534)
==8299== by 0x5658570: NineDevice9_DrawIndexedPrimitiveUP (device9.c:3223)
==8299== by 0x129A8D: fog_test() (NineTests.cpp:1751)
==8299== by 0x2E3EDA: Xnine_fog_Test::TestBody() (NineTests.cpp:23896)
==8299== by 0x32F169: HandleSehExceptionsInMethodIfSupported<testing::Test, void> (gtest.cc:2605)
==8299== by 0x32F169: void testing::internal::HandleExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) (gtest.cc:2641)
==8299== by 0x322976: Run (gtest.cc:2680)
==8299== by 0x322976: testing::Test::Run() (gtest.cc:2670)
==8299== by 0x322B08: Run (gtest.cc:2857)
==8299== by 0x322B08: testing::TestInfo::Run() (gtest.cc:2830)
==8299== by 0x323134: Run (gtest.cc:3011)
==8299== by 0x323134: testing::TestSuite::Run() (gtest.cc:2990)
==8299== by 0x323859: testing::internal::UnitTestImpl::RunAllTests() (gtest.cc:5722)
==8299== by 0x32F6E9: HandleSehExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool> (gtest.cc:2605)
==8299== by 0x32F6E9: bool testing::internal::HandleExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) (gtest.cc:2641)
==8299== Uninitialised value was created by a stack allocation
==8299== at 0x56D40AF: update_vertex_elements (nine_state.c:861)
```
and much more, full log here:[Xnine.fog-valgrind](/uploads/615373a66a6f955870a55bbad03c3f32/Xnine.fog-valgrind)
Specific stack variable that is used uninitialized is `nine_state.c:871 unsigned vtxbuf_holes_map[PIPE_MAX_ATTRIBS];`
Before I figured out this is uninitialized memory, I bisected with one d3d9 trace where I could reliably reproduce the crash to commit 6c4ab0267444b10bee850b30149732a1366d0a0d, but this commit is likely just highlighting the issue.
CC @axeldavy this looks like a nine issue, right? Should we just zero-initialize `vtxbuf_holes_map`? However I also tested with iris and I don't hit any valgrind issues there in this NineTest.https://gitlab.freedesktop.org/mesa/mesa/-/issues/10182Various games fail to launch with gallium nine with same error2023-11-26T18:30:47ZMattia ZorattiVarious games fail to launch with gallium nine with same errorThe title should effectively distinguish this bug report from others and be specific to issue you encounter. When writing the title of the bug report, include a short description of the issue, the hardware/driver(s) affected and applicat...The title should effectively distinguish this bug report from others and be specific to issue you encounter. When writing the title of the bug report, include a short description of the issue, the hardware/driver(s) affected and application(s) affected.
### System information
```
System:
Host: odroidn2 Kernel: 6.1.50-current-meson64 aarch64 bits: 64
compiler: N/A Desktop: Xfce 4.16.0 tk: Gtk 3.24.23 wm: xfwm dm: LightDM
Distro: Ubuntu 22.04.3 LTS (Jammy Jellyfish)
CPU:
Info: quad core (2-mt/2-st) model: ARMv8 v8l variant-1: cortex-a53
variant-2: cortex-a73 bits: 64 type: MST AMCP arch: v8l rev: 4
Speed (MHz): avg: 2272 high: 2400 min/max: 1000/2016:2400 cores: 1: 2016
2: 2016 3: 2400 4: 2400 5: 2400 6: 2400 bogomips: N/A
Features: Use -f option to see features
Graphics:
Device-1: meson-g12a-vpu driver: meson_drm v: N/A bus-ID: N/A
chip-ID: amlogic:ff900000
Device-2: meson-g12a-mali driver: panfrost v: kernel bus-ID: N/A
chip-ID: amlogic:ffe40000
Device-3: meson-g12a-dw-hdmi driver: meson_dw_hdmi v: N/A bus-ID: N/A
chip-ID: amlogic:ff600000
Display: x11 server: X.Org v: 1.21.1.4 compositor: xfwm v: 4.16.1 driver:
X: loaded: modesetting gpu: meson_drm,panfrost,meson_dw_hdmi
display-ID: :0.0 screens: 1
Screen-1: 0 s-res: 2560x1440 s-dpi: 96
Monitor-1: HDMI-1 mapped: HDMI-A-1 model: ITMF27I104QHD res: 2560x1440
dpi: 108 diag: 685mm (27")
OpenGL: renderer: Mali-G52 (Panfrost) v: 3.3 Mesa
24.0~git2311210600.12f627~oibaf~j (git-12f6279 2023-11-21 jammy-oibaf-ppa)
compat-v: 3.3 direct render: Yes
```
#### If applicable
- Wine/Proton version: wine 8.20 staging
### Describe the issue
Lots of games fail to launch when using gallium nine, the error message is always the same:
Fable: the Lost Chapters
fixme:d3d9nine:DRIPresentGroup_GetMultiheadCount (0x1229668)
Splinter Cell 3
fixme:d3d9nine:DRIPresentGroup_GetMultiheadCount (0x1229668)
The Elder Scrolls IV: Oblivion
fixme:d3d9nine:DRIPresentGroup_GetMultiheadCount (0x19688b8)
### Regression
The games were working on older mesa + gallium nine versions (I think around Mesa 22)https://gitlab.freedesktop.org/mesa/mesa/-/issues/9470Hidden & Dangerous Deluxe crashes with Gallium Nine2023-08-10T15:47:58Zmyself600Hidden & Dangerous Deluxe crashes with Gallium Nine### System information
```
System:
Host: manjaro-arm Kernel: 6.3.9-1-MANJARO-ARM arch: aarch64 bits: 64
compiler: gcc v: 12.1.0 Desktop: KDE Plasma v: 5.27.6 tk: Qt v: 5.15.10
wm: kwin_wayland dm: SDDM Distro: Manjaro ARM base...### System information
```
System:
Host: manjaro-arm Kernel: 6.3.9-1-MANJARO-ARM arch: aarch64 bits: 64
compiler: gcc v: 12.1.0 Desktop: KDE Plasma v: 5.27.6 tk: Qt v: 5.15.10
wm: kwin_wayland dm: SDDM Distro: Manjaro ARM base: Arch Linux
CPU:
Info: quad core (2-mt/2-st) model: N/A variant-1: cortex-a53
variant-2: cortex-a72 bits: 64 type: MST AMCP arch: ARMv8 rev: 4
Speed (MHz): avg: 744 high: 1416 min/max: 408/1416:1800 cores: 1: 408
2: 408 3: 408 4: 408 5: 1416 6: 1416 bogomips: N/A
Features: Use -f option to see features
Graphics:
Device-1: display-subsystem driver: rockchip_drm v: N/A bus-ID: N/A
chip-ID: rockchip:display-subsystem
Device-2: rk3399-mali driver: panfrost v: kernel bus-ID: N/A
chip-ID: rockchip:ff9a0000
Display: wayland server: X.org v: 1.21.1.8 with: Xwayland v: 23.1.2
compositor: kwin_wayland driver: X: loaded: modesetting alternate: fbdev
dri: rockchip gpu: rockchip_drm,panfrost display-ID: 0
Monitor-1: eDP-1 res: 1920x1080 size: N/A
API: OpenGL v: 3.1 Mesa 23.0.4 renderer: Mali-T860 (Panfrost)
direct-render: Yes
```
- 32-bit Mesa version: `23.3~git2308020600.4de7e0~oibaf~m`
- Gallium Nine Standalone version: 0.9
- d3d8to9 version: 1.12.0
- Wine version: 8.0.2
### Describe the issue
Game crashes after ESRB notice. It's almost playable with WineD3D, but lags when enemies are around.
### How to reproduce
1. Download and install the (freeware) game from https://www.bestoldgames.net/download/games/hidden-dangerous-deluxe/hidden-dangerous-deluxe.zip
2. Download d3d8.dll from https://github.com/crosire/d3d8to9/releases/latest, d3dx9_43.dll and D3DCompiler_43.dll from https://www.microsoft.com/en-US/download/details.aspx?id=8109 (extract with `7z` or `unar`), and place it all to `~/.wine/drive_c/Program Files/Take2/Hidden and Dangerous Deluxe/bin`
3. Make sure Gallium Nine Standalone is installed and properly working (`wine ninewinecfg`), that is, d3d9-nine.dll and ninewinecfg.exe present in `~/.wine/drive_c/windows/system32` with d3d9.dll symlinked to d3d9-nine.dll, and `/lib/arm-linux-gnueabihf/d3d/d3dadapter9.so.1`
4. Run hde.exe with `WINEDLLOVERRIDES=d3d8=n` (`MESA_EXTENSION_OVERRIDE=-GL_ARB_buffer_storage` is also needed at least on Mali-T860 with Panfrost since Mesa 22.3)
### Log files as attachment
- Apitrace: [hde.trace](/uploads/36ef8c8d9989ec64820c7f7ee7c24310/hde.trace)
### Screenshot
![Screenshot_20230803_184943](https://github.com/iXit/wine-nine-standalone/assets/3542623/dbdf030e-b6f6-4420-b632-26656dba77fc)
### Terminal
```
[pbpro@manjaro-arm ~]$ MESA_EXTENSION_OVERRIDE=-GL_ARB_buffer_storage WINEDLLOVERRIDES=d3d8=n wine ~/'Software/Hidden and Dangerous Deluxe/bin/hde.exe'
Box86 with Dynarec v0.3.1 e8d4ffc built on Jul 31 2023 13:43:04
Box86 with Dynarec v0.3.1 e8d4ffc built on Jul 31 2023 13:43:04
Box86 with Dynarec v0.3.1 e8d4ffc built on Jul 31 2023 13:43:04
002c:err:winediag:getaddrinfo Failed to resolve your host name IP
wine: failed to open L"C:\\windows\\system32\\winemenubuilder.exe": c0000135
002c:err:wineboot:process_run_key Error running cmd L"C:\\windows\\system32\\winemenubuilder.exe -a -r" (126).
0074:err:wineusb:DriverEntry Failed to initialize Unix library, status 0xc0000135.
0074:err:ntoskrnl:ZwLoadDriver failed to create driver L"\\Registry\\Machine\\System\\CurrentControlSet\\Services\\wineusb": c0000135
003c:fixme:service:scmdatabase_autostart_services Auto-start service L"wineusb" failed to start: 126
0094:err:ntoskrnl:ZwLoadDriver failed to create driver L"\\Registry\\Machine\\System\\CurrentControlSet\\Services\\winebus": c0000135
003c:fixme:service:scmdatabase_autostart_services Auto-start service L"winebus" failed to start: 126
Box86 with Dynarec v0.3.1 e8d4ffc built on Jul 31 2023 13:43:04
00dc:fixme:imm:ImeSetActiveContext (00010026, 0): stub
00dc:fixme:imm:ImmReleaseContext (00010020, 00010026): stub
0024:fixme:imm:ImeSetActiveContext (00010064, 1): stub
0024:fixme:imm:ImmReleaseContext (0002005C, 00010064): stub
nine:adapter9:ctor: Your card is at the limit of Gallium Nine requirements. Some games may run into issues because requirements are too tight
Native Direct3D 9 v0.9.0.396-release is active.
For more information visit https://github.com/iXit/wine-nine-standalone
fixme:d3d9nine:DRIPresentGroup_GetMultiheadCount (0x534b08), stub!
fixme:d3d9nine:DRIPresentGroup_GetMultiheadCount (0x534b08), stub!
0024:fixme:toolhelp:CreateToolhelp32Snapshot Unimplemented: heap list snapshot
[pbpro@manjaro-arm ~]$
```
**Edit**: `d3dx9_43` and `d3dcompiler_43` is neededhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/8891Gallium Nine improvement: Reduce overhead of stateblocks2023-04-22T22:19:04ZAxel DavyGallium Nine improvement: Reduce overhead of stateblocksStateblocks are a recording of states in d3d9. They enable to record and apply later state changes.
They can be only a few states, or the whole set of states.
One particularity of d3d9 is that one can change the content of the recorded ...Stateblocks are a recording of states in d3d9. They enable to record and apply later state changes.
They can be only a few states, or the whole set of states.
One particularity of d3d9 is that one can change the content of the recorded states at any moment, which reduces the potential for optimizations.
In addition some of the states can have their content evolve. For example a stateblock might record that a given texture should be in a given slot, but the texture itself can have its internal resource change.
Nine has a worker thread that applies the states for real, and the main thread keeps track of the 'advertised states' that is the value of the states that we need to return if the app requests them (it is also used to replicate the filtering of redundant state application, which has impacts on some corner behaviours). -- off topic: Technically if 'Pure' device is requested (most games do) the main thread is allowed not to remember the states, and we could defer the filtering to the worker thread, but our tests didn't show gains when trying to implement that. Maybe the gain is bigger if stateblocks can work fully in the worker thread. --
The way Nine implements stateblocks is not very efficient. When a stateblock is applied, first all groups of states are checked (nine_state_copy_common), and those that have something recorded are applied on the set of advertised states. Then (nine_context_apply_stateblock) we go though all the groups of states again and apply individually each of them by appending a call for each of them in the command queue of the worker thread. Finally the worker thread will run all the command queue to set individually each state.
While the work of setting the states is unavoidable (main thread and worker thread), the process of appending the calls to the command queue can be optimized.
One way to improve the situation could be to have a copy of what to apply in the worker thread, and thus go through that only once. States which have internal parts that can change (textures, buffers) will need to be handled as is done currently, but that leaves plenty of states.
But since stateblocks states can have their value change, to accommodate for the extreme case where a stateblock would change between each application, this transmission of information to the worker thread shouldn't more heavy than just sending all the states one by one as is done today. For example it is not reasonable to send a copy of the NineStateBlock9 structure everytime the stateblock is changed.
Having a copy of the NineStateBlock9 structure, or an equivalent, in the worker thread, and send all potential updates to it, is a valid solution and probably the fastest. But it will lead to a lot of code.
An alternative could be to record the list of calls to do in the worker thread. Basically add a functionality to record the commands, and then we would do one call to the worker thread to apply the previous command recording. One way to implement it would be to record the size required to store the commands the first time the stateblock is applied. The second time allocate a buffer of this size and use it to record the commands instead of writing in the worker command queue. Then apply. If the states are updated, discard the previous recording. At least this won't be more expensive than what we are doing currently, and we will get gains if the states are not - or rarely - updated.
Both solutions are valid, and will result in faster stateblocks.https://gitlab.freedesktop.org/mesa/mesa/-/issues/8845Gallium Nine improvement: reduce overhead of fixed function rendering2023-04-15T11:21:21ZAxel DavyGallium Nine improvement: reduce overhead of fixed function renderingHere is a list of improvements a contributor can make to improve fixed function rendering on nine.
Fixed function is mainly used for light rendering, or old games, so there hasn't been a huge interest in optimizing it so far.
Here is b...Here is a list of improvements a contributor can make to improve fixed function rendering on nine.
Fixed function is mainly used for light rendering, or old games, so there hasn't been a huge interest in optimizing it so far.
Here is basically how it is handled right now:
Whenever fixed function should be used for a draw call, many rendering states affecting ff are read in order to produce a unique key describing what the shader should do. The shader is build once, and after when we see the key again, the previously compiled shader is reused.
Then, rendering states are checked to see which family of states that fill the shader constants were updated. According to that, a table containing all the shader constants needed is updated.
In all cases, the whole set of shader constants are uploaded to GPU.
The advantage of this approach is maintainability: a lot of rendering states can affect fixed function, and just updating all the time avoided to maintain any logic related to that.
The disadvantage is that any draw call using ff triggers a complete logic (the key computation) and bandwidth was (whole set of shader constants uploaded).
The computation is occuring on the secondary thread, so fortunately it's not too bad.
To improve the situation, here is what could be done:
. Similar to what is done for programmable shaders, the list of constants actually used by the shader could be produced during the first production of the TGSI ff shader. Then the TGSI could be reproduced using shifted offsets for the constants in order to use a compacted set of constants. Then depending on the key, during shader constant upload we would extract the subset needed in a smaller table and upload this one.
. In order to reduce the time spent producing the key, one could precompute most of the key. In the functions that set the relevant states for ff, when needed functions could be called to update parts of the key. This avoid recomputing the whole key. To avoid maintainability difficulties and improve readability, it's better to cut the key in only a few well separated pieces.
. When setting a state relevant for ff shader constants, a function could be called to directly update the constant value at the right position in the table, rather than how we do now.https://gitlab.freedesktop.org/mesa/mesa/-/issues/8716radeonsi: gen7's HyperZ problems with nine and nglide2023-05-06T17:49:46ZMilan Kostićradeonsi: gen7's HyperZ problems with nine and nglideNeed For Speed III (Modern Bundle) defaults to nglide and d3d9:
[![bad.png](https://i.postimg.cc/2SDDgD9r/bad.png)](https://postimg.cc/ykvtSwzb)
[![fine.png](https://i.postimg.cc/JnGVj40c/fine.png)](https://postimg.cc/JDV2L8bG)
Happens e...Need For Speed III (Modern Bundle) defaults to nglide and d3d9:
[![bad.png](https://i.postimg.cc/2SDDgD9r/bad.png)](https://postimg.cc/ykvtSwzb)
[![fine.png](https://i.postimg.cc/JnGVj40c/fine.png)](https://postimg.cc/JDV2L8bG)
Happens ever since this:
https://gitlab.freedesktop.org/mesa/mesa/-/commit/bea0897878e0188b7cc34d33c0ab54a2e160ed4a
Sure nohyperz helps, but happens in a lot of glide games run on nglide/nine, so yeah...
Crysis dx9, constant z-fighting flickerings on the ground everwhere... ever since NIR is enabled, so this:
https://gitlab.freedesktop.org/mesa/mesa/-/commit/75ce078a0aff7fa0f4d6467bea787327da3a4b69
Probably nobody cares, just i tend to forget about these years old regressions... BTW, gfx7https://gitlab.freedesktop.org/mesa/mesa/-/issues/8400r300: nine doesn't correctly place image in a window with dri3 when draw is u...2024-01-11T12:15:18ZPavel Ondračkapavel.ondracka@gmail.comr300: nine doesn't correctly place image in a window with dri3 when draw is used for vs![screenshot](/uploads/8c8940bb69ee9c7a68286011f917e476/screenshot.png)
So when one runs nine on cards that don't have hw vertex shaders, i.e., using the draw module for vertex shader processing (the same codepath can be also exercised ...![screenshot](/uploads/8c8940bb69ee9c7a68286011f917e476/screenshot.png)
So when one runs nine on cards that don't have hw vertex shaders, i.e., using the draw module for vertex shader processing (the same codepath can be also exercised with any card supported by r300 driver and `RADEON_DEBUG=notcl` switch) and using dri3 (dri2 is fine), there are multiple copies of the rendered image in the window. Here its 4 in the screenshot, could be also 9 (depending on the app tested), sometimes the images are also rotated. So it looks like nine can't place the surface into the window properly.
The test app here was Command & Conquer 3 Tiberium Wars Demo, but I can also reproduce with Anno 1404. I can attach D3D9 apitrace if needed (its quite big so not doing it right now).
All works fine with hardware vertex processing or dri2.https://gitlab.freedesktop.org/mesa/mesa/-/issues/8293Current status of Gallium Nine on Panfrost2024-02-25T19:36:50ZAskmewhoCurrent status of Gallium Nine on PanfrostHi folks, during the last week I've been testing gallium nine over panfrost (close to main) with BOX86 on s905y2 and A311D, but this rest reports were made on the S905y2, there is no difference at the end on the results. gallium nine is ...Hi folks, during the last week I've been testing gallium nine over panfrost (close to main) with BOX86 on s905y2 and A311D, but this rest reports were made on the S905y2, there is no difference at the end on the results. gallium nine is overall FAR superior than wine3D while doing emulation, not only is more power efficient, but also frees a lot of cpu cycles to do the actual emulation, providing far better performance than wine3d, and problaby dxvk, something I did not tested on my side. Even then, nine is still faster on several dx9 games compared to dxvk9 on x86_64 platforms, the same will be here (or more).
I got very good results on many games, shifting from radxa zero (s905y2) to radxa zero 2 in order to have something more powerful for comparison and to discard cpu bottlenecks. on many games the A311D device was barely faster (50%) while it-s a far more powerful device than S905Y2. there are situations that going from 800x600 to 1080p almost doesn't change the performance, so, there must be something under the hood impacting on the overall nine performance on panfrost.
this is the setup on the zero, with a bunch of traces made with latest apitrace windows x86 on some games in which nine on panfrost was partially or completely broken. I would make more, but some may be related and would like to know if there is interest on your side to investigate this.
I understand that some games will never be possible to be run on bifrost bc they are not conformant dx9 gpus
3.3 Mesa 23.1.0-devel (git-71a6b53 2023-02-06lunar-oibaf-ppa)
when utilizing a dx8 to dx9 wrapper, the wrapper used was https://github.com/crosire/d3d8to9/releases
flatout, completely broken from launch
https://drive.google.com/file/d/1JnekDi8SMOwBN-d4DUbzG55UV9F_PO5s/view?usp=share_link
prince of persia, sand of time, quite broken right from the menu
https://drive.google.com/file/d/1YUdYZrz3W5RTWVGhOJ4kefSaOFrxSOaa/view?usp=sharing
mafia, a variety of artifacts
https://drive.google.com/file/d/1XDVBemKn7AACZXPR2qRW6XKN01P2aMFP/view?usp=sharing
007 nightfire, used a wrapper here to use nine, completely broken, similar to prince of persia I believe
https://drive.google.com/file/d/1jKeN3usHIJ4pvkGpSZo9gPeFnQLKbx7t/view?usp=sharing
BF1942 dx8 to dx9 wrapper used here
https://drive.google.com/file/d/1aMppfCmj-Wqc_x_fEc-ygolObyYnOpn7/view?usp=sharing
Garfield, DX9 broken/glitchy output ingame.
[d3d9-garfield-panfrost-bifrost.trace](/uploads/3f1cf7cc16f3ec29efda1fdb5fc1c094/d3d9-garfield-panfrost-bifrost.trace)
another trace on main mesa with t860 by myself600
it crash on launch, but replays and dump.
[hde.trace](/uploads/36ef8c8d9989ec64820c7f7ee7c24310/hde.trace)
shantae risky revenge does work but also does a very blurry output, like Aggelos.
https://drive.google.com/file/d/1klJtTxxfhRadTG_8IXfqI0A63sZzY-Ii/view?usp=sharing
a quick new demo of nine on panfrost https://www.youtube.com/watch?v=ElwAjZa8HfE
(note that xmen on the zero 2 was at lower 640x480 by mistake and even then...same perfomance as zero)
@alyssa @okias @lorn10
A more grateful demo on A311D with nine on SonicMania, there are some microstutters, but great overall.
https://youtu.be/YvvxEDGB5Yshttps://gitlab.freedesktop.org/mesa/mesa/-/issues/7866r600/TURKS: FPS information is missing in the game "Mario Kart: Double Dash!!...2022-12-13T13:11:27Zlorn10r600/TURKS: FPS information is missing in the game "Mario Kart: Double Dash!!" with Gallium Nine### Summary
This bug report is somehow an "offspring" of issue #7840 but concerns a different and only minor problem around the final DX9 build [4.0-154](https://en.dolphin-emu.org/download/dev/5d7d8be58e1a71b3fcbb2ed3be78d6a014d4c111/)...### Summary
This bug report is somehow an "offspring" of issue #7840 but concerns a different and only minor problem around the final DX9 build [4.0-154](https://en.dolphin-emu.org/download/dev/5d7d8be58e1a71b3fcbb2ed3be78d6a014d4c111/) of the **dolphin emulator**.
The "on-screen" **FPS information** is missing / not rendered in conjunction with the **r600** driver and **Gallium Nine**. At first I assumed that this might be a limitation in Gallium Nine. But the FPS information is present when a GameCube game like "Mario Kart: Double Dash!!" is played on other hardware like an **Intel HD 2000 iGPU** which uses the crocus driver.
So it looks that this is effectively a small problem of the r600 driver which happens with both the old TGSI and the new NIR path. Everything other is working fine.
For more information please check the apitrace. It is the same like in bug #7840.
This was tested on **Kubuntu 22.04 LTS** and Mesa 23.0.0-devel (git-64d584b 2022-12-05 jammy-oibaf-ppa).
### System information
`inxi -b` output:
```
System:
Host: iMac-test Kernel: 5.15.0-56-generic x86_64 bits: 64
Desktop: KDE Plasma 5.24.7 Distro: Ubuntu 22.04.1 LTS (Jammy Jellyfish)
Machine:
Type: Desktop System: Apple product: iMac12,2 v: 1.0
serial: <superuser required>
Mobo: Apple model: Mac-942B59F58194171B v: iMac12,2
serial: <superuser required> UEFI: Apple v: IM121.88Z.004F.B00.1804101150
date: 04/10/18
CPU:
Info: quad core Intel Core i5-2400 [MCP] speed (MHz): avg: 1600
min/max: 1600/3400
Graphics:
Device-1: Intel 2nd Generation Core Processor Family Integrated Graphics
driver: i915 v: kernel
Device-2: AMD Whistler [Radeon HD 6730M/6770M/7690M XT] driver: radeon
v: kernel
Device-3: Apple FaceTime HD Camera (Built-in) type: USB driver: uvcvideo
Display: x11 server: X.Org v: 1.21.1.3 driver: X:
loaded: ati,modesetting,radeon unloaded: fbdev,vesa gpu: radeon
resolution: 2560x1440~60Hz
OpenGL: renderer: AMD TURKS (DRM 2.50.0 / 5.15.0-56-generic LLVM 15.0.5)
v: 4.5 Mesa 23.0.0-devel (git-64d584b 2022-12-05 jammy-oibaf-ppa)
Network:
Device-1: Broadcom NetXtreme BCM57765 Gigabit Ethernet PCIe driver: tg3
Device-2: Qualcomm Atheros AR93xx Wireless Network Adapter driver: ath9k
Drives:
Local Storage: total: 961.01 GiB used: 120.18 GiB (12.5%)
Info:
Processes: 229 Uptime: 1d 9h 19m Memory: 15.6 GiB used: 3.44 GiB (22.0%)
Shell: Bash inxi: 3.3.13
```
### If applicable
- Wine version: 7.22
### Log files as attachment
Backtrace **Mario Kart: Double Dash!!** (05.12.2022):
https://drive.google.com/file/d/1TNHNHlB2saCh8rWxg2awKlWFIujyAzyS/view?usp=sharing
### Any extra information would be greatly appreciated
Also in this bug report I can confirm that the **OpenGL** renderer in dolphin is not affected. This is only reproducible with the DX9 renderer and Gallium Nine. And as mentioned in my other bug report, WineD3D is unable to work with the dolphin emulator because of several missing D3D features.
Final note, the **dual source blending** capability was enforced in the DX9 renderer. But that feature has no effect in this topic here.https://gitlab.freedesktop.org/mesa/mesa/-/issues/7718Misaligned atomic operation may incur significant performance penalty2023-08-09T12:53:15ZMike LothianMisaligned atomic operation may incur significant performance penaltyI'm seeing the following warnings when compiling with clang. The "significant performance penalty" doesn't sound good
```
../mesa-9999/src/amd/vulkan/radv_query.c:1209:21: warning: misaligned atomic operation may incur significant perfo...I'm seeing the following warnings when compiling with clang. The "significant performance penalty" doesn't sound good
```
../mesa-9999/src/amd/vulkan/radv_query.c:1209:21: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/radv_query.c:1242:24: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/radv_query.c:1243:22: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/radv_query.c:1342:19: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/radv_query.c:1380:16: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/radv_query.c:1381:16: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/radv_query.c:1415:21: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:357:10: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:359:10: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:364:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:537:10: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:539:10: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:544:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:660:4: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:750:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:752:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c:219:23: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/gallium/drivers/zink/zink_batch.c:487:38: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/gallium/frontends/nine/resource9.c:124:9: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/gallium/frontends/nine/resource9.c:82:13: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/gallium/frontends/nine/resource9.c:85:17: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/gallium/frontends/nine/resource9.c:88:17: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/util/disk_cache_os.c:447:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/util/disk_cache_os.c:474:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/util/disk_cache_os.c:490:7: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
../mesa-9999/src/util/disk_cache_os.c:810:4: warning: misaligned atomic operation may incur significant performance penalty; the expected alignment (8 bytes) exceeds the actual alignment (4 bytes) [-Watomic-alignment]
```https://gitlab.freedesktop.org/mesa/mesa/-/issues/7452crocus/Sandy Bridge: The game "A Hat in Time" does not start up with Gallium ...2023-11-02T08:52:08Zlorn10crocus/Sandy Bridge: The game "A Hat in Time" does not start up with Gallium Nine### Summary
This bug report is an "off-spring" of bug #7247 which is r600 related. Although the observed symptoms are different, the original problem cause is most likely the same.
When I start the game **A Hat in Time** on my Sandy Bri...### Summary
This bug report is an "off-spring" of bug #7247 which is r600 related. Although the observed symptoms are different, the original problem cause is most likely the same.
When I start the game **A Hat in Time** on my Sandy Bridge based Intel HD 2000 iGPU the program aborts after some time automatically by itself. Only the start up splash screen of the game is visible for a while.
The underlying problem was already bisected by **Axel Davy** when he fixed this for radeonsi, see MR !9578.
More information can be found in bug #7247, - I quote Axel Davy:
>I remember this game has issues running on radeonsi because the nir generated and kept in memory was too big. The patches I introduced enabled to reduce this issue and make the game run on radeonsi. I guess r600 must be keeping too many version of the nir, just like radeonsi used to.
The game compiles a massive amount of shaders. You must be mistaken about it being 64 bit else it wouldn't have the issue. One workaround would be to not compile the shaders before their first use, basically introducing stuttering when the game uses the shader for the first time, but saving the memory taken by nir.
So far I understand that topic all **NIR** drivers are most likely affected. As mentioned, the problem was fixed around a year ago by Axel Davy for the radeonsi driver and it might be fixed in the near future also for the r600 and eventually the r300 one.
**Addition** (16.12.2022): The corresponding problem was fixed in the **r600** driver with MR !20061, "Store nir shaders serialized to save memory". It looks that this approach is somehow faster than the other variant applied for radeonsi. So there exists no longer any relevant "waiting time" when the game "A Hat in Time" is launched. It is comparable with the launching via WineD3D which also means that my old iMac 12,2 computer outperforms a much newer Ryzen 7 5700U based Asus AiO system. :wink:
An apitrace is also available, see below.
So in the end it looks that all NIR drivers needs a "shader compilation" or a "save memory with NIR shader" tweak. This would also include the iris and the nouveau nv30/nv50/nvc0 drivers.
### System information
`inxi -GSC -xx`
```
System:
Host: iMac-Urs Kernel: 5.15.0-48-generic x86_64 bits: 64 compiler: gcc
v: 11.2.0 Desktop: KDE Plasma 5.24.6 tk: Qt 5.15.3 wm: kwin_x11 dm: SDDM
Distro: Ubuntu 22.04.1 LTS (Jammy Jellyfish)
CPU:
Info: quad core model: Intel Core i5-2400 bits: 64 type: MCP
arch: Sandy Bridge rev: 7 cache: L1: 256 KiB L2: 1024 KiB L3: 6 MiB
Speed (MHz): avg: 1600 min/max: 1600/3400 cores: 1: 1600 2: 1600 3: 1600
4: 1600 bogomips: 24799
Flags: avx ht lm nx pae sse sse2 sse3 sse4_1 sse4_2 ssse3 vmx
Graphics:
Device-1: Intel 2nd Generation Core Processor Family Integrated Graphics
vendor: Apple driver: i915 v: kernel ports: active: none empty: VGA-1
bus-ID: 00:02.0 chip-ID: 8086:0102
Device-2: AMD Whistler [Radeon HD 6730M/6770M/7690M XT] vendor: Apple
driver: radeon v: kernel pcie: speed: 2.5 GT/s lanes: 16 ports:
active: eDP-1 empty: DP-1, DP-2, DP-3, DP-4, VGA-2 bus-ID: 01:00.0
chip-ID: 1002:6740
Device-3: Apple FaceTime HD Camera (Built-in) type: USB driver: uvcvideo
bus-ID: 1-2:3 chip-ID: 05ac:850b
Display: x11 server: X.Org v: 1.21.1.3 compositor: kwin_x11 driver: X:
loaded: ati,modesetting,radeon unloaded: fbdev,vesa gpu: radeon
display-ID: :0 screens: 1
Screen-1: 0 s-res: 2560x1440 s-dpi: 96
Monitor-1: eDP res: 2560x1440 dpi: 109 diag: 685mm (27")
OpenGL: renderer: AMD TURKS (DRM 2.50.0 / 5.15.0-48-generic LLVM 14.0.6)
v: 4.5 Mesa 22.3.0-devel (git-27aa172 2022-10-09 jammy-oibaf-ppa)
direct render: Yes
```
#### If applicable
- Wine version: 7.17
- Kubuntu 22.04 LTS
### Log files as attachment
**A Hat in Time r600 Apitrace** (15.12.2022)
https://drive.google.com/file/d/1AY8mQbs17eUrSC5SV3jMxPhZjxH5XZbx/view?usp=sharing
=> This apitrace is made via TGSI after !20061 landed and with "Precache Shaders" option disabled.
**A Hat in Time r600 Apitrace** (12.09.2022)
https://drive.google.com/file/d/1gMQR_-6fXtb606_nclH44Mt_tQ1i7D5K/view?usp=sharing
=> Original **pre** !20061 apitrace. Consumes on r600 through NIR over **32GB** of main memory (instead of 4GB with TGSI) mostly because the "Precache Shaders" option is enabled.
### Any extra information would be greatly appreciated
The game works with WineD3D but the performance is especially on older systems not so nice.
**Addition** (16.12.2022): The long loading behavior of a level (which is caused by the pre-compiling of a massive amount of shaders) can be also improved by disabling the **Precache Shaders** feature in the game. This feature seems to be normally enabled in GoG game build version 59270 although it is noted that the default is "unchecked" ergo disabled. Whatever, I really should have figured that out sooner:![AHiT_disable_Precache_Shaders](/uploads/0715ce5eb0876ed5153395f6d03a8997/AHiT_disable_Precache_Shaders.png)https://gitlab.freedesktop.org/mesa/mesa/-/issues/6946nine: intel-whl: ERROR: src0 is null2024-03-23T08:55:06ZDavid Heidelbergnine: intel-whl: ERROR: src0 is null - job: https://gitlab.freedesktop.org/okias/mesa/-/jobs/25986259
- tests: https://github.com/iXit/nine-tests
```
...
2022-07-27 22:49:39.458298: succ get_rt_readback Failed to get surface desc, hr 0.
2022-07-27 22:49:39.458305: NIR (S... - job: https://gitlab.freedesktop.org/okias/mesa/-/jobs/25986259
- tests: https://github.com/iXit/nine-tests
```
...
2022-07-27 22:49:39.458298: succ get_rt_readback Failed to get surface desc, hr 0.
2022-07-27 22:49:39.458305: NIR (SSA form) for vertex shader:
2022-07-27 22:49:39.458314: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:39.458322: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:39.458330: name: TTN
2022-07-27 22:49:39.458337: inputs: 3
2022-07-27 22:49:39.458345: outputs: 4
2022-07-27 22:49:39.458352: uniforms: 0
2022-07-27 22:49:39.458359: ubos: 1
2022-07-27 22:49:39.458366: shared: 0
2022-07-27 22:49:39.458373: ray queries: 0
2022-07-27 22:49:39.458380: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:39.458387: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:39.458395: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:39.458402: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:39.458409: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:39.458417: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:39.458424: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:39.458431: decl_var uniform INTERP_MODE_NONE vec4[4] uniform_0 (0, 0, 0)
2022-07-27 22:49:39.458438: decl_var ubo INTERP_MODE_NONE vec4[4] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:39.458446: decl_function main (0 params)
2022-07-27 22:49:39.458453: impl main {
2022-07-27 22:49:39.458460: block block_0:
2022-07-27 22:49:39.458468: /* preds: */
2022-07-27 22:49:39.458475: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:39.458482: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:39.458490: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:39.458498: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:39.458506: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:39.458513: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:39.458520: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:39.458528: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:39.458535: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:39.458543: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:39.458550: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:39.458557: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:39.458564: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:39.458571: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:39.458578: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:39.458585: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:39.458592: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:39.458599: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:39.458666: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:39.458678: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:39.458685: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:39.458692: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:39.458699: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:39.458727: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:39.458734: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:39.458742: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:39.458750: vec4 32 div ssa_26 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:39.458757: vec1 32 div ssa_27 = fsat ssa_26.x
2022-07-27 22:49:39.458764: vec1 32 div ssa_28 = fsat ssa_26.y
2022-07-27 22:49:39.458771: vec1 32 div ssa_29 = fsat ssa_26.z
2022-07-27 22:49:39.458778: vec1 32 div ssa_30 = fsat ssa_26.w
2022-07-27 22:49:39.458785: vec4 32 div ssa_31 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:39.458792: vec1 32 div ssa_32 = fsat ssa_31.x
2022-07-27 22:49:39.458799: vec1 32 div ssa_33 = fsat ssa_31.y
2022-07-27 22:49:39.458807: vec1 32 div ssa_34 = fsat ssa_31.z
2022-07-27 22:49:39.458814: vec1 32 div ssa_35 = fsat ssa_31.w
2022-07-27 22:49:39.458821: vec4 32 div ssa_36 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:39.458830: intrinsic store_output (ssa_36, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:39.458839: vec4 32 div ssa_37 = vec4 ssa_27, ssa_28, ssa_29, ssa_30
2022-07-27 22:49:39.458846: intrinsic store_output (ssa_37, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:39.458853: vec4 32 div ssa_38 = vec4 ssa_32, ssa_33, ssa_34, ssa_35
2022-07-27 22:49:39.458861: intrinsic store_output (ssa_38, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:39.458868: vec4 32 div ssa_39 = vec4 ssa_31.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:39.458876: intrinsic store_output (ssa_39, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:39.458885: /* succs: block_1 */
2022-07-27 22:49:39.458893: block block_1:
2022-07-27 22:49:39.458900: }
2022-07-27 22:49:39.458908: NIR (final form) for vertex shader:
2022-07-27 22:49:39.458916: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:39.458924: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:39.458931: name: TTN
2022-07-27 22:49:39.458939: inputs: 3
2022-07-27 22:49:39.458946: outputs: 4
2022-07-27 22:49:39.458954: uniforms: 0
2022-07-27 22:49:39.458962: ubos: 1
2022-07-27 22:49:39.458970: shared: 0
2022-07-27 22:49:39.458989: ray queries: 0
2022-07-27 22:49:39.458997: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:39.459006: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:39.459015: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:39.459024: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:39.459033: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:39.459067: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:39.459078: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:39.459086: decl_var uniform INTERP_MODE_NONE vec4[4] uniform_0 (0, 0, 0)
2022-07-27 22:49:39.459094: decl_var ubo INTERP_MODE_NONE vec4[4] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:39.459103: decl_function main (0 params)
2022-07-27 22:49:39.459111: impl main {
2022-07-27 22:49:39.459120: block block_0:
2022-07-27 22:49:39.459128: /* preds: */
2022-07-27 22:49:39.459137: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:39.459146: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:39.459154: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:39.459163: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:39.459173: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:39.459203: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:39.459217: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:44.714250: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:44.714387: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:44.714404: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:44.714426: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:44.714436: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:44.714444: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:44.714453: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:44.714461: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:44.714470: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:44.714480: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:44.714489: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:44.714500: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:44.714510: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:44.714518: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:44.714527: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:44.714537: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:44.714545: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:44.714554: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:44.714562: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:44.714571: vec4 32 div ssa_26 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.714580: vec1 32 div ssa_27 = fsat ssa_26.x
2022-07-27 22:49:44.714589: vec1 32 div ssa_28 = fsat ssa_26.y
2022-07-27 22:49:44.714599: vec1 32 div ssa_29 = fsat ssa_26.z
2022-07-27 22:49:44.714608: vec1 32 div ssa_30 = fsat ssa_26.w
2022-07-27 22:49:44.714616: vec4 32 div ssa_31 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.714625: vec1 32 div ssa_32 = fsat ssa_31.x
2022-07-27 22:49:44.714634: vec1 32 div ssa_33 = fsat ssa_31.y
2022-07-27 22:49:44.714643: vec1 32 div ssa_34 = fsat ssa_31.z
2022-07-27 22:49:44.714652: vec1 32 div ssa_35 = fsat ssa_31.w
2022-07-27 22:49:44.714661: vec4 32 div ssa_36 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:44.714696: intrinsic store_output (ssa_36, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.714706: vec4 32 div ssa_37 = vec4 ssa_27, ssa_28, ssa_29, ssa_30
2022-07-27 22:49:44.714714: intrinsic store_output (ssa_37, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.714723: vec4 32 div ssa_38 = vec4 ssa_32, ssa_33, ssa_34, ssa_35
2022-07-27 22:49:44.714730: intrinsic store_output (ssa_38, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.714740: vec4 32 div ssa_39 = vec4 ssa_31.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.714748: intrinsic store_output (ssa_39, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.714757: /* succs: block_1 */
2022-07-27 22:49:44.714766: block block_1:
2022-07-27 22:49:44.714774: }
2022-07-27 22:49:44.714782: VS Output VUE map (23 slots, SSO)
2022-07-27 22:49:44.714791: [0] VARYING_SLOT_PSIZ
2022-07-27 22:49:44.714799: [1] VARYING_SLOT_POS
2022-07-27 22:49:44.714808: [2] VARYING_SLOT_CLIP_DIST0
2022-07-27 22:49:44.714817: [3] VARYING_SLOT_CLIP_DIST1
2022-07-27 22:49:44.714825: [4] VARYING_SLOT_COL0
2022-07-27 22:49:44.714834: [5] VARYING_SLOT_COL1
2022-07-27 22:49:44.714843: [6] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714851: [7] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714859: [8] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714867: [9] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714876: [10] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714883: [11] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714891: [12] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714899: [13] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714908: [14] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714917: [15] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714926: [16] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714934: [17] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714944: [18] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714952: [19] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714960: [20] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714969: [21] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.714978: [22] VARYING_SLOT_VAR16
2022-07-27 22:49:44.714986: Native code for unnamed vertex shader TTN (sha1 48a99faba555e0b3c35cae172e890c310d24424e)
2022-07-27 22:49:44.714996: SIMD8 shader: 29 instructions. 0 loops. 114 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 464 to 352 bytes (24%)
2022-07-27 22:49:44.715005: START B0 (114 cycles)
2022-07-27 22:49:44.715013: mul(8) g24<1>F g4<8,8,1>F g2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715022: mul(8) g25<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715031: mul(8) g26<1>F g4<8,8,1>F g2.2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715040: mul(8) g27<1>F g4<8,8,1>F g2.3<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.715049: mov.sat(8) g16<1>F g8<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715057: mov.sat(8) g17<1>F g9<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715163: mov.sat(8) g18<1>F g10<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715175: mov.sat(8) g19<1>F g11<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715206: mov.sat(8) g20<1>F g12<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715224: mov.sat(8) g21<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715234: mov.sat(8) g22<1>F g14<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715242: mov.sat(8) g23<1>F g15<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715251: mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted };
2022-07-27 22:49:44.715261: mad(8) g28<1>F g24<4,4,1>F g2.4<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715269: mad(8) g29<1>F g25<4,4,1>F g2.5<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715277: mad(8) g30<1>F g26<4,4,1>F g2.6<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715286: mad(8) g31<1>F g27<4,4,1>F g2.7<0,1,0>F g5<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715294: mad(8) g32<1>F g28<4,4,1>F g3.0<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715302: mad(8) g33<1>F g29<4,4,1>F g3.1<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715310: mad(8) g34<1>F g30<4,4,1>F g3.2<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715318: mad(8) g35<1>F g31<4,4,1>F g3.3<0,1,0>F g6<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715326: mad(8) g52<1>F g32<4,4,1>F g3.4<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715334: mad(8) g53<1>F g33<4,4,1>F g3.5<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715342: mad(8) g54<1>F g34<4,4,1>F g3.6<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715352: mad(8) g55<1>F g35<4,4,1>F g3.7<0,1,0>F g7<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.715360: sends(8) nullUD g1UD g52UD 0x02080017 0x00000100
2022-07-27 22:49:44.715368: urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
2022-07-27 22:49:44.715377: sends(8) nullUD g1UD g16UD 0x02080047 0x00000200
2022-07-27 22:49:44.715385: urb MsgDesc: offset 4 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q };
2022-07-27 22:49:44.715393: mov(8) g122<1>F g15<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.715400: sends(8) nullUD g126UD g122UD 0x02080167 0x00000100
2022-07-27 22:49:44.715409: urb MsgDesc: offset 22 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.715419: END B0
2022-07-27 22:49:44.715428: NIR (SSA form) for fragment shader:
2022-07-27 22:49:44.715437: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.715446: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.715454: name: TTN
2022-07-27 22:49:44.715463: inputs: 2
2022-07-27 22:49:44.715470: outputs: 1
2022-07-27 22:49:44.715479: uniforms: 0
2022-07-27 22:49:44.715488: ubos: 1
2022-07-27 22:49:44.715497: shared: 0
2022-07-27 22:49:44.715506: ray queries: 0
2022-07-27 22:49:44.715514: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.715524: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.715534: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.715543: decl_var uniform INTERP_MODE_NONE vec4 uniform_21 (21, 21, 0)
2022-07-27 22:49:44.715553: decl_var ubo INTERP_MODE_NONE vec4[22] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.715563: decl_function main (0 params)
2022-07-27 22:49:44.715580: impl main {
2022-07-27 22:49:44.715589: block block_0:
2022-07-27 22:49:44.715599: /* preds: */
2022-07-27 22:49:44.715608: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.715617: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.715627: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.715637: vec4 32 div ssa_3 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=48, component=0, dest_type=float32 /*160*/, io location=48 slots=1 /*176*/) /* in_1 */
2022-07-27 22:49:44.715646: vec1 32 con ssa_4 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.715702: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.715716: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.715726: vec1 32 div ssa_7 = flrp ssa_6.x, ssa_2.x, ssa_3.x
2022-07-27 22:49:44.715736: vec1 32 div ssa_8 = flrp ssa_6.y, ssa_2.y, ssa_3.x
2022-07-27 22:49:44.715745: vec1 32 div ssa_9 = flrp ssa_6.z, ssa_2.z, ssa_3.x
2022-07-27 22:49:44.715755: vec4 32 div ssa_10 = vec4 ssa_7, ssa_8, ssa_9, ssa_2.w
2022-07-27 22:49:44.715763: intrinsic store_output (ssa_10, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.715773: /* succs: block_1 */
2022-07-27 22:49:44.715783: block block_1:
2022-07-27 22:49:44.715791: }
2022-07-27 22:49:44.715799: NIR (final form) for fragment shader:
2022-07-27 22:49:44.715807: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.715815: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.715824: name: TTN
2022-07-27 22:49:44.715833: inputs: 2
2022-07-27 22:49:44.715842: outputs: 1
2022-07-27 22:49:44.715851: uniforms: 0
2022-07-27 22:49:44.715859: ubos: 1
2022-07-27 22:49:44.715869: shared: 0
2022-07-27 22:49:44.715877: ray queries: 0
2022-07-27 22:49:44.715912: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.715922: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_1 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.715931: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.715939: decl_var uniform INTERP_MODE_NONE vec4 uniform_21 (21, 21, 0)
2022-07-27 22:49:44.715948: decl_var ubo INTERP_MODE_NONE vec4[22] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.715957: decl_function main (0 params)
2022-07-27 22:49:44.715966: impl main {
2022-07-27 22:49:44.715974: block block_0:
2022-07-27 22:49:44.715983: /* preds: */
2022-07-27 22:49:44.715991: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.716000: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.716009: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.716018: vec4 32 div ssa_3 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=48, component=0, dest_type=float32 /*160*/, io location=48 slots=1 /*176*/) /* in_1 */
2022-07-27 22:49:44.716027: vec1 32 con ssa_4 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.716036: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.716045: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.716053: vec1 32 div ssa_7 = flrp ssa_6.x, ssa_2.x, ssa_3.x
2022-07-27 22:49:44.716062: vec1 32 div ssa_8 = flrp ssa_6.y, ssa_2.y, ssa_3.x
2022-07-27 22:49:44.716079: vec1 32 div ssa_9 = flrp ssa_6.z, ssa_2.z, ssa_3.x
2022-07-27 22:49:44.716088: vec4 32 div ssa_10 = vec4 ssa_7, ssa_8, ssa_9, ssa_2.w
2022-07-27 22:49:44.716096: intrinsic store_output (ssa_10, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.716106: /* succs: block_1 */
2022-07-27 22:49:44.716114: block block_1:
2022-07-27 22:49:44.716123: }
2022-07-27 22:49:44.716131: Native code for unnamed fragment shader TTN (sha1 b1f8d995d2d32a1c0ec7911c237f4d1ca4bbf163)
2022-07-27 22:49:44.716161: SIMD8 shader: 9 instructions. 0 loops. 58 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 144 to 112 bytes (22%)
2022-07-27 22:49:44.716170: START B0 (58 cycles)
2022-07-27 22:49:44.716178: pln(8) g11<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716188: pln(8) g9<1>F g5.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716196: pln(8) g13<1>F g6<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716206: pln(8) g126<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716215: pln(8) g8<1>F g7<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.716223: lrp(8) g123<1>F g8<4,4,1>F g11<4,4,1>F g4.4<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.716232: lrp(8) g124<1>F g8<4,4,1>F g9<4,4,1>F g4.5<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.716240: lrp(8) g125<1>F g8<4,4,1>F g13<4,4,1>F g4.6<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.716249: sendc(8) null<1>UW g123<0,1,0>UD 0x88031400
2022-07-27 22:49:44.716257: render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.716266: END B0
2022-07-27 22:49:44.716306: Native code for unnamed fragment shader TTN (sha1 19443fec2f6c2cd45fa7bb5453e75244bc717290)
2022-07-27 22:49:44.716316: SIMD16 shader: 9 instructions. 0 loops. 96 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 144 to 112 bytes (22%)
2022-07-27 22:49:44.716325: START B0 (96 cycles)
2022-07-27 22:49:44.716335: pln(16) g10<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716344: pln(16) g12<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716352: pln(16) g14<1>F g8<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716361: pln(16) g125<1>F g8.4<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716370: pln(16) g16<1>F g9<0,1,0>F g2<8,8,1>F { align1 1H compacted };
2022-07-27 22:49:44.716379: lrp(16) g119<1>F g16<4,4,1>F g10<4,4,1>F g6.4<0,1,0>F { align16 1H };
2022-07-27 22:49:44.716387: lrp(16) g121<1>F g16<4,4,1>F g12<4,4,1>F g6.5<0,1,0>F { align16 1H };
2022-07-27 22:49:44.716397: lrp(16) g123<1>F g16<4,4,1>F g14<4,4,1>F g6.6<0,1,0>F { align16 1H };
2022-07-27 22:49:44.716405: sendc(16) null<1>UW g119<0,1,0>UD 0x90031000
2022-07-27 22:49:44.716414: render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
2022-07-27 22:49:44.716422: END B0
2022-07-27 22:49:44.716431: NIR (SSA form) for vertex shader:
2022-07-27 22:49:44.716440: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.716449: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.716458: name: TTN
2022-07-27 22:49:44.716467: inputs: 3
2022-07-27 22:49:44.716483: outputs: 4
2022-07-27 22:49:44.716491: uniforms: 0
2022-07-27 22:49:44.716500: ubos: 1
2022-07-27 22:49:44.716508: shared: 0
2022-07-27 22:49:44.716516: ray queries: 0
2022-07-27 22:49:44.716525: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.716534: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.716543: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.716552: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.716561: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.716570: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.716580: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.716589: decl_var uniform INTERP_MODE_NONE vec4[8] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.716598: decl_var uniform INTERP_MODE_NONE vec4 uniform_28 (28, 28, 0)
2022-07-27 22:49:44.716607: decl_var ubo INTERP_MODE_NONE vec4[29] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:44.716616: decl_function main (0 params)
2022-07-27 22:49:44.716625: impl main {
2022-07-27 22:49:44.716635: block block_0:
2022-07-27 22:49:44.716643: /* preds: */
2022-07-27 22:49:44.716652: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.716661: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.716670: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.716680: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:44.716690: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:44.716699: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:44.716708: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:44.716717: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:44.716726: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:44.716736: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:44.716744: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:44.716753: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:44.716762: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:44.716769: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:44.716777: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:44.716784: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:44.716792: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:44.716800: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:44.716808: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:44.716816: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:44.716824: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:44.716831: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:44.716839: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:44.716846: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:44.716853: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:44.716860: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:44.716867: vec1 32 con ssa_26 = load_const (0x00000040 = 0.000000)
2022-07-27 22:49:44.716881: vec4 32 con ssa_27 = intrinsic load_ubo (ssa_1, ssa_26) (access=0, align_mul=1073741824, align_offset=64, range_base=64, range=16)
2022-07-27 22:49:44.716891: vec1 32 div ssa_28 = fmul ssa_2.x, ssa_27.z
2022-07-27 22:49:44.716900: vec1 32 con ssa_29 = load_const (0x00000050 = 0.000000)
2022-07-27 22:49:44.716909: vec4 32 con ssa_30 = intrinsic load_ubo (ssa_1, ssa_29) (access=0, align_mul=1073741824, align_offset=80, range_base=80, range=16)
2022-07-27 22:49:44.716918: vec1 32 div ssa_31 = ffma ssa_2.y, ssa_30.z, ssa_28
2022-07-27 22:49:44.716927: vec1 32 con ssa_32 = load_const (0x00000060 = 0.000000)
2022-07-27 22:49:44.716936: vec4 32 con ssa_33 = intrinsic load_ubo (ssa_1, ssa_32) (access=0, align_mul=1073741824, align_offset=96, range_base=96, range=16)
2022-07-27 22:49:44.716945: vec1 32 div ssa_34 = ffma ssa_2.z, ssa_33.z, ssa_31
2022-07-27 22:49:44.716953: vec1 32 con ssa_35 = load_const (0x00000070 = 0.000000)
2022-07-27 22:49:44.716960: vec4 32 con ssa_36 = intrinsic load_ubo (ssa_1, ssa_35) (access=0, align_mul=1073741824, align_offset=112, range_base=112, range=16)
2022-07-27 22:49:44.716969: vec1 32 div ssa_37 = ffma ssa_2.w, ssa_36.z, ssa_34
2022-07-27 22:49:44.716977: vec4 32 div ssa_38 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.716985: vec1 32 div ssa_39 = fsat ssa_38.x
2022-07-27 22:49:44.716994: vec1 32 div ssa_40 = fsat ssa_38.y
2022-07-27 22:49:44.717002: vec1 32 div ssa_41 = fsat ssa_38.z
2022-07-27 22:49:44.717009: vec1 32 div ssa_42 = fsat ssa_38.w
2022-07-27 22:49:44.717018: vec4 32 div ssa_43 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.717027: vec1 32 div ssa_44 = fsat ssa_43.x
2022-07-27 22:49:44.717035: vec1 32 div ssa_45 = fsat ssa_43.y
2022-07-27 22:49:44.717043: vec1 32 div ssa_46 = fsat ssa_43.z
2022-07-27 22:49:44.717051: vec1 32 div ssa_47 = fsat ssa_43.w
2022-07-27 22:49:44.717059: vec1 32 div ssa_48 = fabs ssa_37
2022-07-27 22:49:44.717067: vec1 32 con ssa_49 = load_const (0x000001c0 = 0.000000)
2022-07-27 22:49:44.717075: vec4 32 con ssa_50 = intrinsic load_ubo (ssa_1, ssa_49) (access=0, align_mul=1073741824, align_offset=448, range_base=448, range=16)
2022-07-27 22:49:44.717083: vec1 32 div ssa_51 = fneg ssa_48
2022-07-27 22:49:44.717092: vec1 32 div ssa_52 = fadd ssa_50.x, ssa_51
2022-07-27 22:49:44.717100: vec1 32 div ssa_53 = fmul ssa_52, ssa_50.y
2022-07-27 22:49:44.717109: vec1 32 div ssa_54 = fsat ssa_53
2022-07-27 22:49:44.717117: vec4 32 div ssa_55 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:44.717126: intrinsic store_output (ssa_55, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.717135: vec4 32 div ssa_56 = vec4 ssa_39, ssa_40, ssa_41, ssa_42
2022-07-27 22:49:44.717143: intrinsic store_output (ssa_56, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.717152: vec4 32 div ssa_57 = vec4 ssa_44, ssa_45, ssa_46, ssa_47
2022-07-27 22:49:44.717160: intrinsic store_output (ssa_57, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.717169: vec4 32 div ssa_58 = vec4 ssa_54, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.717177: intrinsic store_output (ssa_58, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.717185: /* succs: block_1 */
2022-07-27 22:49:44.717194: block block_1:
2022-07-27 22:49:44.717203: }
2022-07-27 22:49:44.717243: NIR (final form) for vertex shader:
2022-07-27 22:49:44.717252: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.717260: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.717269: name: TTN
2022-07-27 22:49:44.717278: inputs: 3
2022-07-27 22:49:44.717286: outputs: 4
2022-07-27 22:49:44.717295: uniforms: 0
2022-07-27 22:49:44.717303: ubos: 1
2022-07-27 22:49:44.717311: shared: 0
2022-07-27 22:49:44.717319: ray queries: 0
2022-07-27 22:49:44.717327: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.717335: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.717343: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.717351: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.717359: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.717367: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.717375: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.717383: decl_var uniform INTERP_MODE_NONE vec4[8] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.717391: decl_var uniform INTERP_MODE_NONE vec4 uniform_28 (28, 28, 0)
2022-07-27 22:49:44.717399: decl_var ubo INTERP_MODE_NONE vec4[29] uniform_0@0 (0, 0, 0)
2022-07-27 22:49:44.717407: decl_function main (0 params)
2022-07-27 22:49:44.717414: impl main {
2022-07-27 22:49:44.717422: block block_0:
2022-07-27 22:49:44.717430: /* preds: */
2022-07-27 22:49:44.717437: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.717445: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.717453: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.717461: vec4 32 con ssa_3 = intrinsic load_ubo (ssa_1, ssa_1) (access=0, align_mul=1073741824, align_offset=0, range_base=0, range=16)
2022-07-27 22:49:44.717468: vec1 32 div ssa_4 = fmul ssa_2.x, ssa_3.x
2022-07-27 22:49:44.717477: vec1 32 div ssa_5 = fmul ssa_2.x, ssa_3.y
2022-07-27 22:49:44.717484: vec1 32 div ssa_6 = fmul ssa_2.x, ssa_3.z
2022-07-27 22:49:44.717492: vec1 32 div ssa_7 = fmul ssa_2.x, ssa_3.w
2022-07-27 22:49:44.717500: vec1 32 con ssa_8 = load_const (0x00000010 = 0.000000)
2022-07-27 22:49:44.717507: vec4 32 con ssa_9 = intrinsic load_ubo (ssa_1, ssa_8) (access=0, align_mul=1073741824, align_offset=16, range_base=16, range=16)
2022-07-27 22:49:44.717515: vec1 32 div ssa_10 = ffma ssa_2.y, ssa_9.x, ssa_4
2022-07-27 22:49:44.717523: vec1 32 div ssa_11 = ffma ssa_2.y, ssa_9.y, ssa_5
2022-07-27 22:49:44.717531: vec1 32 div ssa_12 = ffma ssa_2.y, ssa_9.z, ssa_6
2022-07-27 22:49:44.717539: vec1 32 div ssa_13 = ffma ssa_2.y, ssa_9.w, ssa_7
2022-07-27 22:49:44.717546: vec1 32 con ssa_14 = load_const (0x00000020 = 0.000000)
2022-07-27 22:49:44.717554: vec4 32 con ssa_15 = intrinsic load_ubo (ssa_1, ssa_14) (access=0, align_mul=1073741824, align_offset=32, range_base=32, range=16)
2022-07-27 22:49:44.717562: vec1 32 div ssa_16 = ffma ssa_2.z, ssa_15.x, ssa_10
2022-07-27 22:49:44.717569: vec1 32 div ssa_17 = ffma ssa_2.z, ssa_15.y, ssa_11
2022-07-27 22:49:44.717576: vec1 32 div ssa_18 = ffma ssa_2.z, ssa_15.z, ssa_12
2022-07-27 22:49:44.717584: vec1 32 div ssa_19 = ffma ssa_2.z, ssa_15.w, ssa_13
2022-07-27 22:49:44.717592: vec1 32 con ssa_20 = load_const (0x00000030 = 0.000000)
2022-07-27 22:49:44.717600: vec4 32 con ssa_21 = intrinsic load_ubo (ssa_1, ssa_20) (access=0, align_mul=1073741824, align_offset=48, range_base=48, range=16)
2022-07-27 22:49:44.717608: vec1 32 div ssa_22 = ffma ssa_2.w, ssa_21.x, ssa_16
2022-07-27 22:49:44.717655: vec1 32 div ssa_23 = ffma ssa_2.w, ssa_21.y, ssa_17
2022-07-27 22:49:44.717664: vec1 32 div ssa_24 = ffma ssa_2.w, ssa_21.z, ssa_18
2022-07-27 22:49:44.717671: vec1 32 div ssa_25 = ffma ssa_2.w, ssa_21.w, ssa_19
2022-07-27 22:49:44.717678: vec1 32 con ssa_26 = load_const (0x00000040 = 0.000000)
2022-07-27 22:49:44.717685: vec4 32 con ssa_27 = intrinsic load_ubo (ssa_1, ssa_26) (access=0, align_mul=1073741824, align_offset=64, range_base=64, range=16)
2022-07-27 22:49:44.717692: vec1 32 div ssa_28 = fmul ssa_2.x, ssa_27.z
2022-07-27 22:49:44.717699: vec1 32 con ssa_29 = load_const (0x00000050 = 0.000000)
2022-07-27 22:49:44.717705: vec4 32 con ssa_30 = intrinsic load_ubo (ssa_1, ssa_29) (access=0, align_mul=1073741824, align_offset=80, range_base=80, range=16)
2022-07-27 22:49:44.717713: vec1 32 div ssa_31 = ffma ssa_2.y, ssa_30.z, ssa_28
2022-07-27 22:49:44.717720: vec1 32 con ssa_32 = load_const (0x00000060 = 0.000000)
2022-07-27 22:49:44.717728: vec4 32 con ssa_33 = intrinsic load_ubo (ssa_1, ssa_32) (access=0, align_mul=1073741824, align_offset=96, range_base=96, range=16)
2022-07-27 22:49:44.717735: vec1 32 div ssa_34 = ffma ssa_2.z, ssa_33.z, ssa_31
2022-07-27 22:49:44.717742: vec1 32 con ssa_35 = load_const (0x00000070 = 0.000000)
2022-07-27 22:49:44.717749: vec4 32 con ssa_36 = intrinsic load_ubo (ssa_1, ssa_35) (access=0, align_mul=1073741824, align_offset=112, range_base=112, range=16)
2022-07-27 22:49:44.717757: vec1 32 div ssa_37 = ffma ssa_2.w, ssa_36.z, ssa_34
2022-07-27 22:49:44.717764: vec4 32 div ssa_38 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.717772: vec1 32 div ssa_39 = fsat ssa_38.x
2022-07-27 22:49:44.717779: vec1 32 div ssa_40 = fsat ssa_38.y
2022-07-27 22:49:44.717786: vec1 32 div ssa_41 = fsat ssa_38.z
2022-07-27 22:49:44.717793: vec1 32 div ssa_42 = fsat ssa_38.w
2022-07-27 22:49:44.717800: vec4 32 div ssa_43 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.717807: vec1 32 div ssa_44 = fsat ssa_43.x
2022-07-27 22:49:44.717815: vec1 32 div ssa_45 = fsat ssa_43.y
2022-07-27 22:49:44.717822: vec1 32 div ssa_46 = fsat ssa_43.z
2022-07-27 22:49:44.717828: vec1 32 div ssa_47 = fsat ssa_43.w
2022-07-27 22:49:44.717835: vec1 32 div ssa_48 = fabs ssa_37
2022-07-27 22:49:44.717842: vec1 32 con ssa_49 = load_const (0x000001c0 = 0.000000)
2022-07-27 22:49:44.717850: vec4 32 con ssa_50 = intrinsic load_ubo (ssa_1, ssa_49) (access=0, align_mul=1073741824, align_offset=448, range_base=448, range=16)
2022-07-27 22:49:44.717858: vec1 32 div ssa_51 = fneg ssa_48
2022-07-27 22:49:44.717865: vec1 32 div ssa_52 = fadd ssa_50.x, ssa_51
2022-07-27 22:49:44.717873: vec1 32 div ssa_53 = fmul ssa_52, ssa_50.y
2022-07-27 22:49:44.717881: vec1 32 div ssa_54 = fsat ssa_53
2022-07-27 22:49:44.717888: vec4 32 div ssa_55 = vec4 ssa_22, ssa_23, ssa_24, ssa_25
2022-07-27 22:49:44.717895: intrinsic store_output (ssa_55, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.717905: vec4 32 div ssa_56 = vec4 ssa_39, ssa_40, ssa_41, ssa_42
2022-07-27 22:49:44.717913: intrinsic store_output (ssa_56, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.717920: vec4 32 div ssa_57 = vec4 ssa_44, ssa_45, ssa_46, ssa_47
2022-07-27 22:49:44.717929: intrinsic store_output (ssa_57, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.717937: vec4 32 div ssa_58 = vec4 ssa_54, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.717944: intrinsic store_output (ssa_58, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.717987: /* succs: block_1 */
2022-07-27 22:49:44.717997: block block_1:
2022-07-27 22:49:44.718004: }
2022-07-27 22:49:44.718011: VS Output VUE map (23 slots, SSO)
2022-07-27 22:49:44.718018: [0] VARYING_SLOT_PSIZ
2022-07-27 22:49:44.718025: [1] VARYING_SLOT_POS
2022-07-27 22:49:44.718033: [2] VARYING_SLOT_CLIP_DIST0
2022-07-27 22:49:44.718040: [3] VARYING_SLOT_CLIP_DIST1
2022-07-27 22:49:44.718047: [4] VARYING_SLOT_COL0
2022-07-27 22:49:44.718054: [5] VARYING_SLOT_COL1
2022-07-27 22:49:44.718061: [6] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718067: [7] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718075: [8] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718084: [9] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718092: [10] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718100: [11] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718106: [12] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718113: [13] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718120: [14] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718128: [15] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718135: [16] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718143: [17] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718150: [18] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718158: [19] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718166: [20] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718173: [21] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.718180: [22] VARYING_SLOT_VAR16
2022-07-27 22:49:44.718187: Native code for unnamed vertex shader TTN (sha1 447eb0bb1111eb6ee202eb90e872aa08ec4e3291)
2022-07-27 22:49:44.718194: SIMD8 shader: 34 instructions. 0 loops. 130 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 544 to 432 bytes (21%)
2022-07-27 22:49:44.718202: START B0 (130 cycles)
2022-07-27 22:49:44.718210: mul(8) g27<1>F g7<8,8,1>F g2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718218: mul(8) g28<1>F g7<8,8,1>F g2.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718225: mul(8) g29<1>F g7<8,8,1>F g2.2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718233: mul(8) g30<1>F g7<8,8,1>F g2.3<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718241: mul(8) g43<1>F g7<8,8,1>F g4.2<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718248: mov.sat(8) g19<1>F g11<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718255: mov.sat(8) g20<1>F g12<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718262: mov.sat(8) g21<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718270: mov.sat(8) g22<1>F g14<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718278: mov.sat(8) g23<1>F g15<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718287: mov.sat(8) g24<1>F g16<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718295: mov.sat(8) g25<1>F g17<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718304: mov.sat(8) g26<1>F g18<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.718312: mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted };
2022-07-27 22:49:44.718321: mad(8) g31<1>F g27<4,4,1>F g2.4<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718329: mad(8) g32<1>F g28<4,4,1>F g2.5<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718338: mad(8) g33<1>F g29<4,4,1>F g2.6<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718354: mad(8) g34<1>F g30<4,4,1>F g2.7<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718364: mad(8) g44<1>F g43<4,4,1>F g4.6<0,1,0>F g8<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718373: mad(8) g35<1>F g31<4,4,1>F g3.0<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718381: mad(8) g36<1>F g32<4,4,1>F g3.1<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718388: mad(8) g37<1>F g33<4,4,1>F g3.2<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718397: mad(8) g38<1>F g34<4,4,1>F g3.3<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718406: mad(8) g45<1>F g44<4,4,1>F g5.2<0,1,0>F g9<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718415: mad(8) g60<1>F g35<4,4,1>F g3.4<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718424: mad(8) g61<1>F g36<4,4,1>F g3.5<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718433: mad(8) g62<1>F g37<4,4,1>F g3.6<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718441: mad(8) g63<1>F g38<4,4,1>F g3.7<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718450: mad(8) g46<1>F g45<4,4,1>F g5.6<0,1,0>F g10<4,4,1>F { align16 1Q };
2022-07-27 22:49:44.718458: add(8) g55<1>F g6<0,1,0>F -(abs)g46<8,8,1>F { align1 1Q };
2022-07-27 22:49:44.718466: mul.sat(8) g122<1>F g55<8,8,1>F g6.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.718474: sends(8) nullUD g1UD g60UD 0x02080017 0x00000100
2022-07-27 22:49:44.718482: urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
2022-07-27 22:49:44.718491: sends(8) nullUD g1UD g19UD 0x02080047 0x00000200
2022-07-27 22:49:44.718500: urb MsgDesc: offset 4 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q };
2022-07-27 22:49:44.718507: sends(8) nullUD g126UD g122UD 0x02080167 0x00000100
2022-07-27 22:49:44.718516: urb MsgDesc: offset 22 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.718524: END B0
2022-07-27 22:49:44.718533: NIR (SSA form) for vertex shader:
2022-07-27 22:49:44.718540: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.718549: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.718558: name: TTN
2022-07-27 22:49:44.718568: inputs: 3
2022-07-27 22:49:44.718576: outputs: 4
2022-07-27 22:49:44.718585: uniforms: 0
2022-07-27 22:49:44.718593: shared: 0
2022-07-27 22:49:44.718601: ray queries: 0
2022-07-27 22:49:44.718609: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.718618: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.718626: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.718634: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.718641: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.718649: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.718657: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.718665: decl_function main (0 params)
2022-07-27 22:49:44.718674: impl main {
2022-07-27 22:49:44.718683: block block_0:
2022-07-27 22:49:44.718691: /* preds: */
2022-07-27 22:49:44.718724: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.718735: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.718743: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.718752: vec4 32 div ssa_3 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.718761: vec1 32 div ssa_4 = fsat ssa_3.x
2022-07-27 22:49:44.718768: vec1 32 div ssa_5 = fsat ssa_3.y
2022-07-27 22:49:44.718776: vec1 32 div ssa_6 = fsat ssa_3.z
2022-07-27 22:49:44.718783: vec1 32 div ssa_7 = fsat ssa_3.w
2022-07-27 22:49:44.718790: vec4 32 div ssa_8 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.718798: vec1 32 div ssa_9 = fsat ssa_8.x
2022-07-27 22:49:44.718805: vec1 32 div ssa_10 = fsat ssa_8.y
2022-07-27 22:49:44.718812: vec1 32 div ssa_11 = fsat ssa_8.z
2022-07-27 22:49:44.718819: vec1 32 div ssa_12 = fsat ssa_8.w
2022-07-27 22:49:44.718826: intrinsic store_output (ssa_2, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.718834: vec4 32 div ssa_13 = vec4 ssa_4, ssa_5, ssa_6, ssa_7
2022-07-27 22:49:44.718841: intrinsic store_output (ssa_13, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.718848: vec4 32 div ssa_14 = vec4 ssa_9, ssa_10, ssa_11, ssa_12
2022-07-27 22:49:44.718855: intrinsic store_output (ssa_14, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.718862: vec4 32 div ssa_15 = vec4 ssa_8.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.718869: intrinsic store_output (ssa_15, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.718876: /* succs: block_1 */
2022-07-27 22:49:44.718884: block block_1:
2022-07-27 22:49:44.718891: }
2022-07-27 22:49:44.718900: NIR (final form) for vertex shader:
2022-07-27 22:49:44.718908: shader: MESA_SHADER_VERTEX
2022-07-27 22:49:44.718916: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.718925: name: TTN
2022-07-27 22:49:44.718933: inputs: 3
2022-07-27 22:49:44.718941: outputs: 4
2022-07-27 22:49:44.718949: uniforms: 0
2022-07-27 22:49:44.718958: shared: 0
2022-07-27 22:49:44.718966: ray queries: 0
2022-07-27 22:49:44.718974: decl_var shader_in INTERP_MODE_FLAT vec4 in_0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
2022-07-27 22:49:44.718983: decl_var shader_in INTERP_MODE_FLAT vec4 in_1 (VERT_ATTRIB_GENERIC1.xyzw, 16, 0)
2022-07-27 22:49:44.718991: decl_var shader_in INTERP_MODE_FLAT vec4 in_2 (VERT_ATTRIB_GENERIC2.xyzw, 17, 0)
2022-07-27 22:49:44.718999: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (VARYING_SLOT_POS.xyzw, 0, 0)
2022-07-27 22:49:44.719007: decl_var shader_out INTERP_MODE_FLAT vec4 out_1 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.719015: decl_var shader_out INTERP_MODE_FLAT vec4 out_2 (VARYING_SLOT_COL1.xyzw, 2, 0)
2022-07-27 22:49:44.719024: decl_var shader_out INTERP_MODE_FLAT vec4 out_3 (VARYING_SLOT_VAR16.xyzw, 48, 0)
2022-07-27 22:49:44.719032: decl_function main (0 params)
2022-07-27 22:49:44.719041: impl main {
2022-07-27 22:49:44.719049: block block_0:
2022-07-27 22:49:44.719057: /* preds: */
2022-07-27 22:49:44.719065: vec4 32 con ssa_0 = undefined
2022-07-27 22:49:44.719074: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.719081: vec4 32 div ssa_2 = intrinsic load_input (ssa_1) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
2022-07-27 22:49:44.719098: vec4 32 div ssa_3 = intrinsic load_input (ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=16 slots=1 /*144*/)
2022-07-27 22:49:44.719106: vec1 32 div ssa_4 = fsat ssa_3.x
2022-07-27 22:49:44.719114: vec1 32 div ssa_5 = fsat ssa_3.y
2022-07-27 22:49:44.719123: vec1 32 div ssa_6 = fsat ssa_3.z
2022-07-27 22:49:44.719130: vec1 32 div ssa_7 = fsat ssa_3.w
2022-07-27 22:49:44.719138: vec4 32 div ssa_8 = intrinsic load_input (ssa_1) (base=2, component=0, dest_type=float32 /*160*/, io location=17 slots=1 /*145*/)
2022-07-27 22:49:44.719146: vec1 32 div ssa_9 = fsat ssa_8.x
2022-07-27 22:49:44.719154: vec1 32 div ssa_10 = fsat ssa_8.y
2022-07-27 22:49:44.719162: vec1 32 div ssa_11 = fsat ssa_8.z
2022-07-27 22:49:44.719171: vec1 32 div ssa_12 = fsat ssa_8.w
2022-07-27 22:49:44.719200: intrinsic store_output (ssa_2, ssa_1) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.719211: vec4 32 div ssa_13 = vec4 ssa_4, ssa_5, ssa_6, ssa_7
2022-07-27 22:49:44.719220: intrinsic store_output (ssa_13, ssa_1) (base=1, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=1 slots=1 /*129*/, xfb() /*0*/, xfb2() /*0*/) /* out_1 */
2022-07-27 22:49:44.719229: vec4 32 div ssa_14 = vec4 ssa_9, ssa_10, ssa_11, ssa_12
2022-07-27 22:49:44.719237: intrinsic store_output (ssa_14, ssa_1) (base=2, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=2 slots=1 /*130*/, xfb() /*0*/, xfb2() /*0*/) /* out_2 */
2022-07-27 22:49:44.719245: vec4 32 div ssa_15 = vec4 ssa_8.w, ssa_0.y, ssa_0.z, ssa_0.w
2022-07-27 22:49:44.719254: intrinsic store_output (ssa_15, ssa_1) (base=48, wrmask=x /*1*/, component=0, src_type=float32 /*160*/, io location=48 slots=1 /*176*/, xfb() /*0*/, xfb2() /*0*/) /* out_3 */
2022-07-27 22:49:44.719263: /* succs: block_1 */
2022-07-27 22:49:44.719271: block block_1:
2022-07-27 22:49:44.719279: }
2022-07-27 22:49:44.719288: VS Output VUE map (23 slots, SSO)
2022-07-27 22:49:44.719297: [0] VARYING_SLOT_PSIZ
2022-07-27 22:49:44.719306: [1] VARYING_SLOT_POS
2022-07-27 22:49:44.719315: [2] VARYING_SLOT_CLIP_DIST0
2022-07-27 22:49:44.719323: [3] VARYING_SLOT_CLIP_DIST1
2022-07-27 22:49:44.719331: [4] VARYING_SLOT_COL0
2022-07-27 22:49:44.719339: [5] VARYING_SLOT_COL1
2022-07-27 22:49:44.719348: [6] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719356: [7] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719364: [8] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719373: [9] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719382: [10] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719390: [11] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719399: [12] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719408: [13] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719416: [14] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719425: [15] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719433: [16] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719442: [17] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719450: [18] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719458: [19] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719466: [20] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719474: [21] BRW_VARYING_SLOT_PAD
2022-07-27 22:49:44.719483: [22] VARYING_SLOT_VAR16
2022-07-27 22:49:44.719491: Native code for unnamed vertex shader TTN (sha1 ffb696f9ce71a921f6078357aeddcf510fa5d013)
2022-07-27 22:49:44.719500: SIMD8 shader: 17 instructions. 0 loops. 80 cycles. 0:0 spills:fills, 3 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 272 to 160 bytes (41%)
2022-07-27 22:49:44.719508: START B0 (80 cycles)
2022-07-27 22:49:44.719517: mov.sat(8) g14<1>F g6<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719548: mov.sat(8) g15<1>F g7<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719558: mov.sat(8) g16<1>F g8<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719566: mov.sat(8) g17<1>F g9<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719574: mov.sat(8) g18<1>F g10<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719582: mov.sat(8) g19<1>F g11<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719590: mov.sat(8) g20<1>F g12<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719597: mov.sat(8) g21<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719604: mov(8) g27<1>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719612: mov(8) g28<1>F g3<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719621: mov(8) g29<1>F g4<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719629: mov(8) g30<1>F g5<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719637: mov(8) g126<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted };
2022-07-27 22:49:44.719646: sends(8) nullUD g1UD g27UD 0x02080017 0x00000100
2022-07-27 22:49:44.719654: urb MsgDesc: offset 1 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
2022-07-27 22:49:44.719663: sends(8) nullUD g1UD g14UD 0x02080047 0x00000200
2022-07-27 22:49:44.719670: urb MsgDesc: offset 4 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q };
2022-07-27 22:49:44.719679: mov(8) g122<1>F g13<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.719686: sends(8) nullUD g126UD g122UD 0x02080167 0x00000100
2022-07-27 22:49:44.719694: urb MsgDesc: offset 22 SIMD8 write mlen 1 ex_mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.719703: END B0
2022-07-27 22:49:44.719711: NIR (SSA form) for fragment shader:
2022-07-27 22:49:44.719719: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.719727: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.719735: name: TTN
2022-07-27 22:49:44.719743: inputs: 1
2022-07-27 22:49:44.719752: outputs: 1
2022-07-27 22:49:44.719760: uniforms: 0
2022-07-27 22:49:44.719768: ubos: 1
2022-07-27 22:49:44.719776: shared: 0
2022-07-27 22:49:44.719785: ray queries: 0
2022-07-27 22:49:44.719793: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.719801: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.719809: decl_var uniform INTERP_MODE_NONE vec4[2] uniform_21 (21, 21, 0)
2022-07-27 22:49:44.719818: decl_var ubo INTERP_MODE_NONE vec4[23] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.719826: decl_function main (0 params)
2022-07-27 22:49:44.719835: impl main {
2022-07-27 22:49:44.719843: block block_0:
2022-07-27 22:49:44.719851: /* preds: */
2022-07-27 22:49:44.719860: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.719868: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.719877: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.719886: vec4 32 div ssa_3 = intrinsic load_frag_coord () ()
2022-07-27 22:49:44.719908: vec1 32 con ssa_4 = load_const (0x00000160 = 0.000000)
2022-07-27 22:49:44.719918: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.719926: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=352, range_base=352, range=16)
2022-07-27 22:49:44.719935: vec1 32 div ssa_7 = fneg ssa_3.z
2022-07-27 22:49:44.719943: vec1 32 div ssa_8 = fadd ssa_6.x, ssa_7
2022-07-27 22:49:44.719951: vec1 32 div ssa_9 = fmul ssa_8, ssa_6.y
2022-07-27 22:49:44.719959: vec1 32 div ssa_10 = fsat ssa_9
2022-07-27 22:49:44.719966: vec1 32 con ssa_11 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.719974: vec4 32 con ssa_12 = intrinsic load_ubo (ssa_5, ssa_11) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.719982: vec1 32 div ssa_13 = flrp ssa_12.x, ssa_2.x, ssa_10
2022-07-27 22:49:44.719990: vec1 32 div ssa_14 = flrp ssa_12.y, ssa_2.y, ssa_10
2022-07-27 22:49:44.719998: vec1 32 div ssa_15 = flrp ssa_12.z, ssa_2.z, ssa_10
2022-07-27 22:49:44.720006: vec4 32 div ssa_16 = vec4 ssa_13, ssa_14, ssa_15, ssa_2.w
2022-07-27 22:49:44.720014: intrinsic store_output (ssa_16, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.720022: /* succs: block_1 */
2022-07-27 22:49:44.720031: block block_1:
2022-07-27 22:49:44.720039: }
2022-07-27 22:49:44.720047: NIR (final form) for fragment shader:
2022-07-27 22:49:44.720056: shader: MESA_SHADER_FRAGMENT
2022-07-27 22:49:44.720064: source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
2022-07-27 22:49:44.720073: name: TTN
2022-07-27 22:49:44.720082: inputs: 1
2022-07-27 22:49:44.720090: outputs: 1
2022-07-27 22:49:44.720099: uniforms: 0
2022-07-27 22:49:44.720107: ubos: 1
2022-07-27 22:49:44.720115: shared: 0
2022-07-27 22:49:44.720123: ray queries: 0
2022-07-27 22:49:44.720132: decl_var shader_in INTERP_MODE_SMOOTH vec4 in_0 (VARYING_SLOT_COL0.xyzw, 1, 0)
2022-07-27 22:49:44.720140: decl_var shader_out INTERP_MODE_FLAT vec4 out_0 (FRAG_RESULT_DATA0.xyzw, 8, 0)
2022-07-27 22:49:44.720149: decl_var uniform INTERP_MODE_NONE vec4[2] uniform_21 (21, 21, 0)
2022-07-27 22:49:44.720157: decl_var ubo INTERP_MODE_NONE vec4[23] uniform_0 (0, 0, 0)
2022-07-27 22:49:44.720166: decl_function main (0 params)
2022-07-27 22:49:44.720174: impl main {
2022-07-27 22:49:44.720183: block block_0:
2022-07-27 22:49:44.720192: /* preds: */
2022-07-27 22:49:44.720200: vec2 32 div ssa_0 = intrinsic load_barycentric_pixel () (interp_mode=1)
2022-07-27 22:49:44.720208: vec1 32 con ssa_1 = load_const (0x00000000 = 0.000000)
2022-07-27 22:49:44.720217: vec4 32 div ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=1, component=0, dest_type=float32 /*160*/, io location=1 slots=1 /*129*/) /* in_0 */
2022-07-27 22:49:44.720224: vec4 32 div ssa_3 = intrinsic load_frag_coord () ()
2022-07-27 22:49:44.720232: vec1 32 con ssa_4 = load_const (0x00000160 = 0.000000)
2022-07-27 22:49:44.720240: vec1 32 con ssa_5 = load_const (0x00000001 = 0.000000)
2022-07-27 22:49:44.720248: vec4 32 con ssa_6 = intrinsic load_ubo (ssa_5, ssa_4) (access=0, align_mul=1073741824, align_offset=352, range_base=352, range=16)
2022-07-27 22:49:44.720257: vec1 32 div ssa_7 = fneg ssa_3.z
2022-07-27 22:49:44.720265: vec1 32 div ssa_8 = fadd ssa_6.x, ssa_7
2022-07-27 22:49:44.720288: vec1 32 div ssa_9 = fmul ssa_8, ssa_6.y
2022-07-27 22:49:44.720296: vec1 32 div ssa_10 = fsat ssa_9
2022-07-27 22:49:44.720304: vec1 32 con ssa_11 = load_const (0x00000150 = 0.000000)
2022-07-27 22:49:44.720312: vec4 32 con ssa_12 = intrinsic load_ubo (ssa_5, ssa_11) (access=0, align_mul=1073741824, align_offset=336, range_base=336, range=16)
2022-07-27 22:49:44.720319: vec1 32 div ssa_13 = flrp ssa_12.x, ssa_2.x, ssa_10
2022-07-27 22:49:44.720350: vec1 32 div ssa_14 = flrp ssa_12.y, ssa_2.y, ssa_10
2022-07-27 22:49:44.720360: vec1 32 div ssa_15 = flrp ssa_12.z, ssa_2.z, ssa_10
2022-07-27 22:49:44.720368: vec4 32 div ssa_16 = vec4 ssa_13, ssa_14, ssa_15, ssa_2.w
2022-07-27 22:49:44.720376: intrinsic store_output (ssa_16, ssa_1) (base=8, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=4 slots=1 /*132*/, xfb() /*0*/, xfb2() /*0*/) /* out_0 */
2022-07-27 22:49:44.720384: /* succs: block_1 */
2022-07-27 22:49:44.720393: block block_1:
2022-07-27 22:49:44.720401: }
2022-07-27 22:49:44.720410: Native code for unnamed fragment shader TTN (sha1 79cb4fc7ba74b8716c799ae02334d0968987c41c)
2022-07-27 22:49:44.720418: SIMD8 shader: 11 instructions. 0 loops. 74 cycles. 0:0 spills:fills, 1 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 176 to 128 bytes (27%)
2022-07-27 22:49:44.720427: START B0 (74 cycles)
2022-07-27 22:49:44.720435: pln(8) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720443: pln(8) g9<1>F g6.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720452: pln(8) g13<1>F g7<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720461: pln(8) g126<1>F g7.4<0,1,0>F g2<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720470: mov(8) g8<1>F null<8,8,1>F { align1 1Q };
2022-07-27 22:49:44.720478: ERROR: src0 is null
2022-07-27 22:49:44.720487: add(8) g2<1>F g5<0,1,0>F -g8<8,8,1>F { align1 1Q compacted };
2022-07-27 22:49:44.720496: mul.sat(8) g3<1>F g2<8,8,1>F g5.1<0,1,0>F { align1 1Q compacted };
2022-07-27 22:49:44.720505: lrp(8) g123<1>F g3<4,4,1>F g11<4,4,1>F g4.4<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.720513: lrp(8) g124<1>F g3<4,4,1>F g9<4,4,1>F g4.5<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.720521: lrp(8) g125<1>F g3<4,4,1>F g13<4,4,1>F g4.6<0,1,0>F { align16 1Q };
2022-07-27 22:49:44.720530: sendc(8) null<1>UW g123<0,1,0>UD 0x88031400
2022-07-27 22:49:44.720539: render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
2022-07-27 22:49:44.720547: END B0
2022-07-27 22:49:44.720555: NineTests: ../src/intel/compiler/brw_fs_generator.cpp:2620: int fs_generator::generate_code(const cfg_t*, int, shader_stats, const brw::performance&, brw_compile_stats*): Assertion `validated' failed.
2022-07-27 22:49:44.720565: ./NineTests.sh: line 3: 293 Aborted INTEL_DEBUG=shaders ./NineTests
```https://gitlab.freedesktop.org/mesa/mesa/-/issues/6360nine: [feature request] creating d3d11 runtime with feature level 9_32022-04-26T12:01:27ZFilip Gawinnine: [feature request] creating d3d11 runtime with feature level 9_3I remember that in past I was able to debug d3d9 on laptop (GMA 4500MHD) with renderdoc on windows7.
Renderdoc never supported d3d9, so implementing this should help with debugging nine via modern tools.
CC @axeldavyI remember that in past I was able to debug d3d9 on laptop (GMA 4500MHD) with renderdoc on windows7.
Renderdoc never supported d3d9, so implementing this should help with debugging nine via modern tools.
CC @axeldavyhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/5994[Feature Request] nine: option to force supersampling in driver2023-03-12T13:18:26ZFilip Gawin[Feature Request] nine: option to force supersampling in driverI really like this feature from Amd's Catalyst, using it together with old games gives boost in visual quality.
@axeldavyI really like this feature from Amd's Catalyst, using it together with old games gives boost in visual quality.
@axeldavyhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/5690radeonsi hyperz issue2023-05-08T15:20:22ZRoman Elshinradeonsi hyperz issueThere are rendering issues in Saboteur game with nine in some places, and AMD_DEBUG=nohyperz resolves it, d3d trace: https://drive.google.com/file/d/1QM3g29m5Xs5R-cfQpIHNUrrXnGcvjke1/view?usp=sharing , issue reproducible with d3dretrace ...There are rendering issues in Saboteur game with nine in some places, and AMD_DEBUG=nohyperz resolves it, d3d trace: https://drive.google.com/file/d/1QM3g29m5Xs5R-cfQpIHNUrrXnGcvjke1/view?usp=sharing , issue reproducible with d3dretrace at least on polaris11 and gcn1 cards.
P.S. original report https://github.com/iXit/Mesa-3D/issues/356https://gitlab.freedesktop.org/mesa/mesa/-/issues/5068nine: compile warnings2022-07-21T18:09:48ZMike Blumenkrantznine: compile warningson gcc11 release build
```
[859/908] Compiling C object src/gallium/frontends/nine/libnine_st.a.p/nine_memory_helper.c.o
../src/gallium/frontends/nine/nine_memory_helper.c: In function ‘nine_allocate’:
../src/gallium/frontends/nine/nine_...on gcc11 release build
```
[859/908] Compiling C object src/gallium/frontends/nine/libnine_st.a.p/nine_memory_helper.c.o
../src/gallium/frontends/nine/nine_memory_helper.c: In function ‘nine_allocate’:
../src/gallium/frontends/nine/nine_memory_helper.c:427:45: warning: ‘best_region’ is used uninitialized [-Wuninitialized]
427 | struct nine_memfd_file_region *region, *best_region, *new_region;
| ^~~~~~~~~~~
../src/gallium/frontends/nine/nine_memory_helper.c:426:42: warning: ‘best_memfd_file’ is used uninitialized [-Wuninitialized]
426 | struct nine_memfd_file *memfd_file, *best_memfd_file;
```Axel DavyAxel Davyhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/5066Crocus: Gen4 Gallium Nine application crashes and broken graphics2024-03-15T17:49:05ZFierelierCrocus: Gen4 Gallium Nine application crashes and broken graphics### System information
- OS: Arch Linux
- GPU: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (primary) [8086:2a02] (rev 0c)
- Kernel version: Linux 5.12.15-arch1-1 \#1 SMP PREEMPT Wed, 07 Jul 2021 23:35:29 +0000 x8...### System information
- OS: Arch Linux
- GPU: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (primary) [8086:2a02] (rev 0c)
- Kernel version: Linux 5.12.15-arch1-1 \#1 SMP PREEMPT Wed, 07 Jul 2021 23:35:29 +0000 x86_64 GNU/Linux
- Mesa version: Mesa 21.3.0-devel (git-12d18abfe7)
- Xserver version (if applicable): X.Org X Server 1.20.12
- Desktop manager and compositor: No DM, no compositor
- Wine version: wine-6.12
- wine-nine version: [v0.8.0.385-release](https://github.com/iXit/wine-nine-standalone/releases/tag/v0.8)
### Describe the issue
When using Gallium Nine, most games using DX9 do not launch. Games that do have broken graphics. I use a 32-bit wine prefix.
### Log files as attachment
- Output of `dmesg` - **Not attached, as no recent output at occurrence.**
- Backtrace - Removed as the backtraces attached were unrelated.
- Gpu hang details - Not applicable.
### Screenshots/video files (if applicable)
**FlatOut 1**
![flatout1](/uploads/cd386edbfe17a1eab760bab2b71b14a5/flatout1.png)
**FlatOut 2**
![flatout2](/uploads/2ffc20d3a71edb9e0b2193e8fdd9db28/flatout2.png)https://gitlab.freedesktop.org/mesa/mesa/-/issues/5062nine: potential optimization ideas2023-04-22T20:24:02ZMike Blumenkrantznine: potential optimization ideasLooking at CSMT CPU usage, there's a couple things that would significantly improve performance:
* defer all destructors (textures+buffers) using CSMT
- this would mean that all the refcount subtraction occurs in CSMT, meaning that a h...Looking at CSMT CPU usage, there's a couple things that would significantly improve performance:
* defer all destructors (textures+buffers) using CSMT
- this would mean that all the refcount subtraction occurs in CSMT, meaning that a huge amount of refcounting could be eliminated; in Left 4 Dead 2, these account for about 25% of all CPU usage by CSMT
* (potentially) rework userbuf constant upload to use the threaded context uploader, which would reduce memory usage
- not sure if viable given that this is copying regions into the buffer, so they'd have to be flattened ahead of timehttps://gitlab.freedesktop.org/mesa/mesa/-/issues/4742Codespell report for "mesa" (on fossies.org)2023-03-16T20:22:08ZjschleusCodespell report for "mesa" (on fossies.org)The FOSS server [fossies.org](https://fossies.org) - supporting also the [mesa](https://fossies.org/mesa) project - offers among others a feature named "[Source code misspelling reports](https://fossies.org/features.html#codespell)". Suc...The FOSS server [fossies.org](https://fossies.org) - supporting also the [mesa](https://fossies.org/mesa) project - offers among others a feature named "[Source code misspelling reports](https://fossies.org/features.html#codespell)". Such reports are normally only generated on request, but as Fossies administrator I have just created for testing purposes such a [codespell](https://github.com/codespell-project/codespell) based analysis for the mesa GitLab "main" version:
https://fossies.org/linux/test/mesa-main.tar.gz/codespell.html
That version independent URL hopefully always redirects to the report for the latest "main" version identified by the short GitLab commit ID and a year-month-day string (YYMMDD) representing the according git pull date (mostly = commit date). The data are residing within a special restricted "test" folder that isn't really integrated into the standard Fossies services and should also not be accessible to search engines. The report should be available at least for some weeks and is continuously updated (currently every four hours).
Although after a first review some obviously wrong matches ("False Positives") are already filtered out (ignored) please inform me if you find more of them so that I can exclude them if applicable.
In particular, I also had trouble deciding which subdirectories should be excluded as external source code and which should not.
Errors without a determined context (marked by a "?") should be given special attention, as they may be contained in the source code itself. They are easy to find by sorting the spelling error context type by clicking the bold "T" in the column header (if JavaScript is enabled).
Just for information there are also three supplemental pages showing some used "codespell" [configuration details](https://fossies.org/linux/test/mesa-main.tar.gz/codespell_conf.html), all obvious [false positives](https://fossies.org/linux/test/mesa-main.tar.gz/codespell_fps.html) and an [misspelling history](https://fossies.org/linux/test/mesa-main.tar.gz/codespell_hist.html) (log).
Ok, spelling corrections certainly have a low priority, but they may also contribute to the overall quality of a software project.
Edit: I just changed the cloned and analyzed repo from "master" to "main" (the new default). The originally given "master" URLs will still be reachable for a week; a significant difference is actually only the for "main" missing [misspelling history of "master"](https://fossies.org/linux/test/mesa-master.tar.gz/codespell_hist.html) that does not yet exist for "main" due to the changeoverhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/4713[nine] FF13: Invisible keyboard key icons in save/load screen2021-04-30T14:24:28ZMasanori Kakura[nine] FF13: Invisible keyboard key icons in save/load screen### System information
- OS: Ubuntu 21.04
- GPU: Radeon Vega 3 Graphics
- Kernel version: 5.11.0-16-lowlatency
- Mesa version: 21.1.0-rc3
- Xserver version: 1.20.11
- Desktop manager and compositor: LXQt/Openbox, No compositor
- Proton ...### System information
- OS: Ubuntu 21.04
- GPU: Radeon Vega 3 Graphics
- Kernel version: 5.11.0-16-lowlatency
- Mesa version: 21.1.0-rc3
- Xserver version: 1.20.11
- Desktop manager and compositor: LXQt/Openbox, No compositor
- Proton version: 5.13-6
- wine-nine-standalone version: 0.8
### Describe the issue
When using nine, keyboard key icons in save/load screen are not visible.
wined3d (expected rendering):
![ff13-loadscreen-wined3d](/uploads/8c3135ba7dafbf6d810d94d2504065ea/ff13-loadscreen-wined3d.png)
nine (broken rendering):
![ff13-loadscreen-nine](/uploads/b4f4dd2806d3dbe1e322e514c8a8c7a7/ff13-loadscreen-nine.png)
### Log files as attachment
- [apitrace (nine)](/uploads/de85bd9679b13c0eb7997238f3ae0f07/nine-ff13-invisible-key-icons-trace-nine.trace.xz): Even when using wined3d for replaying, the icons are invisible.
- [apitrace (wined3d)](/uploads/d51b9077c3621743c487c150eb96ce3b/nine-ff13-invisible-key-icons-trace-wined3d.trace.xz): Even when using nine for replaying, the icons are visible.
- [NINE_DEBUG=all WINEDEBUG=+d3d9nine output](/uploads/54fea9ae7e3879e0b6afe06b02bfc632/nine-ff13-invisible-key-icons-log.txt.xz)