- 20 May, 2021 18 commits
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Usually, nir_opt_constant_folding will get rid of any load_constant intrinsics which might possibly be pushed but there are rare cases where we can still end up with them. Better to handle them. Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Part-of: <!10571>
(cherry picked from commit c01354d5) -
Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Part-of: <!10571>
(cherry picked from commit 24b3e71f) -
They can't be encoded. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: 
Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <!10841>
(cherry picked from commit 3013670d) -
This prevents read buffer overflows in dup_vertex(), when draw stages allocate extra shader outputs after the vertex buffers are allocated. The original issue can be exercised with upcoming piglit/tests/general/vertex-fallbacks.c test. Reviewed-by:
Roland Scheidegger <sroland@vmware.com> Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org> Part-of: <!10836> (cherry picked from commit 250605c5)
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There is a regression that made it impossible to export gem handles with write access. That is, a client may export gem handles of each buffer plane, then export dmabuf fds using these handles, and mmap these dmabuf in a different process (this is what Chromium does). After !4861, it became impossible as mmap resulted in EACCESS error as slightly different approach was taken for exporting these gem handles. This CL fixes exporting gem handles (which are exported from dmabuf fds) by adding the DRM_RDWR flag. Cc: mesa-stable Fixes #3119 Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!10850>
(cherry picked from commit 5eaf8b59) -
The start offset of the vertex samplers isn't zero, but the indexing of the passed in views array is still zero based. Use the correct indexing variable to fix vertex sampler setup. Cc: <mesa-stable@lists.freedesktop.org> Fixes: 81ab9fe2 ("etnaviv: handle NULL views in set_sampler_views") Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <!10724> (cherry picked from commit 92ed827f)
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There is a regression that made it impossible to export gem handles with write access. That is, a client may export gem handles of each buffer plane, then export dmabuf fds using these handles, and mmap these dmabuf in a different process (this is what Chromium does). After !4861, it became impossible as mmap resulted in EACCESS error as slightly different approach was taken for exporting these gem handles. This CL fixes exporting gem handles (which are exported from dmabuf fds) by adding the DRM_RDWR flag. Cc: mesa-stable Fixes #3119 Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!10851>
(cherry picked from commit b74898ef) -
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Closes: #4777 Fixes: 4e861ac4 ("i915g: Add more optimizations") Fixes: f34fd58e ("i915g: implement unfenced relocs for textures using tiling bits") Fixes: beaf039f ("i915g: cleanup static state calculation, part 1") Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <!10811> (cherry picked from commit 3e74bbf6)
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BOs in the cache are chronological, so we try oldest BOs first. That means if we find the oldest BO is busy, likely every BO is busy, and we should bail early. This dramatically reduces the useless cycles spent in bo_wait. I studied the BO cache of the following drivers, all of which handle this correctly: iris, lima, etnaviv, freedreno, vc4, v3d, v3dv. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <!10794>
(cherry picked from commit 77d04989) -
This fixes some new cts tests that exercise blitting between compressed and uncompressed formats. Cc: mesa-stable Signed-off-by:
Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!10830>
(cherry picked from commit 72fd1260) -
a fence applies to all the submitted cmdbufs, so it's necessary to do the flush which creates the user fence after all the cmdbufs have been processed in order to avoid creating a fence that only applies to the first cmdbuf Fixes: b38879f8 ("vallium: initial import of the vulkan frontend") Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <!10795> (cherry picked from commit cf3f17a6)
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Closes: #4772 Fixes: 2a06423c ("gallium: add CAPs to support HW atomic counters. (v3)") Reviewed-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!10776>
(cherry picked from commit f88dd7ed) -
The initial value needs to be taken from the instruction that is being moved over, not the one to be moved. Additionally the parameter of this function was removed because it was misleading. Setting it to any value other than source_idx would cause register_demand to be initialized incorrectly. (Instead, the maximum demand among the covered instructions would need to be determined.) Reviewed-by:
Daniel Schürmann <daniel@schuermann.dev> Cc: mesa-stable Part-of: <!10644> (cherry picked from commit 50ba919d)
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Previously, changes in total_demand_clause were not always propagated to total_demand. For instance, clause moves do not change the local register demand at the end of a clause, yet they may still affect the total maximum. Reviewed-by:
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Fixes: 752eefdb ("intel/isl: Refactor isl_surf_get_ccs_surf") Signed-off-by:
Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: 
Nanley Chery <nanley.g.chery@intel.com>
Part-of: <!10768>
(cherry picked from commit 343d90b6)
Conflicts:
src/intel/isl/isl.c -
Signed-off-by:
Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 2adb3372 ("nir,radv/aco: add and use pass to lower make available/visible barriers")
Part-of: <!10766>
(cherry picked from commit 2c3e2d69) -
this screen object can never, ever be accessed like this in a resource, as it may have previously been replaced by a wrapper (e.g., driver trace) which will then explode when it is accessed directly instead, keep a separate screen ref on the resource which is known to be the actual driver object and not a wrapper Fixes: 0a497eb1 ("iris: make resources take a ref on the screen object") Reviewed-by: Lionel Landwerlin lionel.g.landwerlin@intel.com Part-of: <!10632> (cherry picked from commit eb63c7de) Conflicts: src/gallium/drivers/iris/iris_resource.c
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- 19 May, 2021 7 commits
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Do not leak pipe resource if scanout resource creation fails. Fixes: bf697319 ("v3d: Allow the UIF modifier with renderonly.") Reviewed-by:
Iago Toral Quiroga <itoral@igalia.com> Signed-off-by:
Juan A. Suarez Romero <jasuarez@igalia.com> Part-of: <!10643> (cherry picked from commit 66bf683c)
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Without this check, if we receive any attribs from the client, we either find an X11/XCB screen fd in there, or we keep going until we end up in random bits of memory and crash. Fixes: 4aebd86f ("egl/x11: pick the user requested screen") Signed-off-by:
Eric Engestrom <eric@engestrom.ch> Reviewed-by:
Adam Jackson <ajax@redhat.com> Part-of: <!10717> (cherry picked from commit 2af08bf7)
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Cc: mesa-stable Signed-off-by:
Karol Herbst <kherbst@redhat.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com> Reviewed-by:
Pierre Moreau <dev@pmoreau.org>
Part-of: <!8765>
(cherry picked from commit 98280e83) -
Fixes the following building error: FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so ... ld.lld: error: undefined symbol: nir_lower_fragcolor >>> referenced by pan_assemble.c:81 (external/mesa/src/gallium/drivers/panfrost/pan_assemble.c:81) Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org> Fixes: 1fd35630 ("nir: add lowering pass for fragcolor -> fragdata") Acked-by:
Rob Clark <robclark@freedesktop.org> Part-of: <!10712> (cherry picked from commit 2736ae04)
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We have to unwind the lod into the scalar path correctly. Fixes a crash with renderdoc demo Fixes: e168d148 ("gallivm/nir: handle non-uniform texture offsets") Reviewed-By:
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <!10676>
(cherry picked from commit 83a05caa) -
Dylan Baker authored
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Adam Jackson authored
Caught this with an LTO build: [1465/1465] Linking target src/gallium/targets/dri/libgallium_dri.so In function ‘spirv_shader_delete’, inlined from ‘nir_to_spirv’ at ../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3907:7: ../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3916:4: warning: ‘free’ called on pointer ‘block_1394’ with nonzero offset 48 [-Wfree-nonheap-object] 3916 | FREE(s); | ^ ../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c: In function ‘nir_to_spirv’: ../src/util/ralloc.c:133:18: note: returned from ‘malloc’ 133 | void *block = malloc(align64(size + sizeof(ralloc_header), | ^ Since s->words is allocated on the same ralloc context we can simplify further by freeing the context all at once. Reviewed-by:Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <!10857>
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- 07 May, 2021 1 commit
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Pierre-Eric Pelloux-Prayer authored
This is a workaround for issue 4605: alignment should always be at least 256 but in this specific case it seems to be 0. Skip the check in this case to "fix" the regression. Closes: #4605 Part-of: <!10680>
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- 06 May, 2021 2 commits
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Dylan Baker authored
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Dylan Baker authored
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- 05 May, 2021 12 commits
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When I last time fixed this, I missed that continuing here would make us leak pointers in the translate state, which is what made this avoid a crash in the first place. That's not great, we need to set *some* pointer in this case. The obvious option would be NULL, but that means that the translate-code also needs to support NULL-pointers here. Instead, let's point to a small, static buffer that contains enough zero-data for the largest possible vertex attribute. This avoids having to add more NULL-checks. Fixes: a8e8204b ("gallium/u_vbuf: support NULL-resources") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!7773> (cherry picked from commit a2d09169)
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Dylan Baker authored
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Dylan Baker authored
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The build-finished event is also triggered when there's an error. I somehow got the second argument wrong, and ended up ignoring the case. This can lead to new exceptions being thrown due to missing files, that ends up hiding the real problem. Fixes: 64a4ba9e ("docs: add an extension to generate redirects") Reviewed-by:
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There's a recently discovered HW bug affecting hardware at least as far back as Skylake where, if the LOD is out-of-bounds for any SIMD lane, then garbage may be returned in all SIMD lanes. The easy solution is to set lower_txs_lod so that we always have a constant LOD of 0 which we know a priori is always in-bounds. Fortunately, not many shaders actually use textureSize() with LOD. Shader-db results on Ice Lake: total instructions in shared programs: 19948537 -> 19948564 (<.01%) instructions in affected programs: 3859 -> 3886 (0.70%) helped: 0 HURT: 7 One of the shaders is in Civilization: Beyond Earth, and the rest are all in Civilization VI. Reviewed-by:Francisco Jerez <currojerez@riseup.net> Reviewed-by:
Anuj Phogat <anuj.phogat@gmail.com> Cc: mesa-stable@lists.freedesktop.org Part-of: <!10538> (cherry picked from commit 05a37e24)
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a0.x is written as a half-reg, but just interpreting it as "hr61.x" will result in it overlapping with r30.z in merged mode, which is not what the hardware does at all. This introduced a spurious dependency on a write to r30.z which resulted in an assert tripping. Just pretend it's a full reg instead. This fixes spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs with the new RA. Fixes: 0f78c324 ("freedreno/ir3: post-RA sched pass") Part-of: <!10591> (cherry picked from commit e597f8b1)
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RADV doesn't try to keep anything 16 or 32 byte aligned. RADV also seems to create better code for some reason. fossil-db (Sienna Cichlid): Totals from 37693 (30.93% of 121873) affected shaders: SGPRs: 1762792 -> 1785504 (+1.29%); split: -1.01%, +2.30% VGPRs: 1761032 -> 1760808 (-0.01%); split: -0.09%, +0.07% SpillSGPRs: 55793 -> 56011 (+0.39%); split: -3.49%, +3.88% SpillVGPRs: 16766 -> 16387 (-2.26%); split: -3.99%, +1.73% CodeSize: 82902228 -> 82781608 (-0.15%); split: -0.29%, +0.14% Scratch: 3024896 -> 2987008 (-1.25%); split: -3.08%, +1.83% MaxWaves: 919794 -> 920302 (+0.06%); split: +0.09%, -0.03% shader-db (Sienna Cichlid): Totals from affected shaders: SGPRS: 3976 -> 3976 (0.00 %) VGPRS: 3392 -> 3392 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 178792 -> 178980 (0.11 %) bytes Max Waves: 1389 -> 1389 (0.00 %) Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: -
Dylan Baker authored
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If radv_pipeline_cache_insert_shaders() finds a GS copy shader in the cache, it will free the variant in gs_variants and replace it with the one in the cache. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: mesa-stable Part-of: <!10433> (cherry picked from commit d6894b64)
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Dylan Baker authored
so later patches will apply cleanly
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If depth bias is enabled but zero values used, they were never emitted to the command buffer because they are equal to the default values. Previously, they were always emitted when the bound DS attachment changed. This should fix some sort of Z fighting with Dota2 on all GPUs. This also fixes a different issue (ie. some occlusion queries failures) on GFX6 because CLEAR_STATE is not used on that chip. Fixes: 8a47422d ("radv: do not scale the depth bias for D16_UNORM depth surfaces") Cc: 21.1 mesa-stable Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <!10310> (cherry picked from commit 1d354269)
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Dylan Baker authored
So that later patches will apply cleanly
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