1. 23 Aug, 2018 1 commit
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  12. 19 Dec, 2017 1 commit
  13. 09 Nov, 2017 1 commit
    • Dave Airlie's avatar
      gallium: add CAPs to support HW atomic counters. (v3) · 2a06423c
      Dave Airlie authored
      This looks like an evergreen specific feature, but with atomic
      counters AMD have hw specific counters they use instead of operating
      on buffers directly. These are separate to the buffer atomics,
      so require different limits and code paths.
      
      I've left the CAP for atomic type extensible in case someone
      else has a variant on this sort of thing (freedreno maybe?)
      and needs to change it.
      
      This adds all the CAPs required to add support for those atomic
      counters, along with a related CAP for limiting the number of
      output resources.
      
      I'd like to land this and the st patch then I can start to
      upstream the evergreen support for these and other GL4.x features.
      
      v2: drop the ATOMIC_COUNTER_MODE cap, just use the return
      from the HW counters. If 0 we use the current mode.
      v3: fix some rebase errors (Gert Wollny)
      Reviewed-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
      Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
      Tested-By: Gert Wollny's avatarGert Wollny <gw.fossdev@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      2a06423c
  14. 06 Nov, 2017 1 commit
  15. 01 Nov, 2017 1 commit
  16. 10 Oct, 2017 1 commit
    • Eric Anholt's avatar
      gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4. · ac0051a5
      Eric Anholt authored
      Because vc4 can control the order that tiles are rasterized in, we can use
      it to implement overlapping blits using normal drawing and
      GL_ARB_texture_barrier, as long as we can tell the kernel what order to
      render the tiles in.
      
      This commit introduces the core gallium support, vc4 changes will follow.
      
      v2: Fix on the simulator.
      v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
      v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
      v5: Drop vc4 changes from this commit, for clarity.
      
      Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
      ac0051a5
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