- 16 May, 2022 40 commits
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SO was always enabled before this change. That meant, after a call to tu_CmdBindTransformFeedbackBuffersEXT to emit VPC_SO_BUFFER_SIZE, any draw call (from the same render pass, in a different render pass, or in a different cmdbuf) could potentially cause writes to the SO buffers regardless of whether the draw is inside xfb begin/end or not. I choose to emit VPC_SO_DISABLE instead of using stateobjs like freedreno does only because it is simpler. It is not clear to me which is more efficient to HW. This also fixes double SO writes for gmem rendering. While tu6_tile_render_begin was careful to disable SO for the draw pass, tu6_emit_tile_select re-enabled it. dEQP-VK.transform_feedback.* still passes. It fixes dEQP-GLES3.functional.transform_feedback.* on angle. Part-of: <!16502>
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It seems fine to advertise msaa in sampledImageIntegerSampleCounts. dEQP-VK.rasterization.rasterization_order_attachment_access.format_integer.* goes from NotSupported to Pass for more test cases. Part-of: <mesa/mesa!16487>
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Fixes: 3e85a0c9 ("ac/surface: define gfx11 modifiers") ../../src/amd/common/ac_surface.c: In function 'ac_get_supported_modifiers': ../../src/amd/common/ac_surface.c:421:47: error: 'AMD_FMT_MOD_TILE_GFX11_256K_R_X' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_GFX9_64K_R_X'? 421 | unsigned swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | AMD_FMT_MOD_TILE_GFX9_64K_R_X ../../src/amd/common/ac_surface.c:421:47: note: each undeclared identifier is reported only once for each function it appears in In file included from ../../src/amd/common/ac_surface.c:31: ../../src/amd/common/ac_surface.c:424:61: error: 'AMD_FMT_MOD_TILE_VER_GFX11' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_VER_GFX10'? 424 | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) | | ^~~~~~~~~~~~~~~~~~~~~~~~~~ ../../src/amd/common/ac_drm_fourcc.h:75:21: note: in definition of macro 'AMD_FMT_MOD_SET' 75 | ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) | ^~~~~ Signed-off-by:
Yonggang Luo <luoyonggang@gmail.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <mesa/mesa!16373>
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Fixes: b261ac1a ("ac/gpu_info: print all IP versions reported by the kernel") ``` ../../src/amd/common/ac_gpu_info.c ../../src/amd/common/ac_gpu_info.c: In function 'ac_query_gpu_info': ../../src/amd/common/ac_gpu_info.c:545:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_major' 545 | info->ip[ip_type].ver_major = ip_info.hw_ip_version_major; | ^ ../../src/amd/common/ac_gpu_info.c:546:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_minor' 546 | info->ip[ip_type].ver_minor = ip_info.hw_ip_version_minor; | ^ ``` Signed-off-by:
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Fixes: 11c28d97 ("ac: add ac_nir_optimize_outputs, a NIR version of ac_optimize_vs_outputs") ``` FAILED: src/amd/common/libamd_common.a.p/ac_nir_opt_outputs.c.obj "cl" "-Isrc\amd\common\libamd_common.a.p" "-Isrc\amd\common" "-I..\mesa\src\amd\common" "-Iinclude" "-I..\mesa\include" "-Isrc" "-I..\mesa\src" "-Isrc\mapi" "-I..\mesa\src\mapi" "-Isrc\mesa" "-I..\mesa\src\mesa" "-I..\mesa\src\gallium\include" "-Isrc\gallium\auxiliary" "-I..\mesa\src\gallium\auxiliary" "-Isrc\compiler" "-I..\mesa\src\compiler" "-Isrc\amd" "-I..\mesa\src\amd" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\contrib\elftoolchain\common" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\contrib\elftoolchain\libelf" "-I..\mesa\subprojects\libelf-lfg-win32-1.1.0-freebsd-12.1.0\sys" "-Isrc\util" "-I..\mesa\src\util" "-Isubprojects\zlib-1.2.11" "-I..\mesa\subprojects\zlib-1.2.11" "-Isrc\compiler\nir" "-I..\mesa\src\compiler\nir" "/MT" "/nologo" "/showIncludes" "/utf-8" "/W3" "/WX" "/std:c11" "/O2" "/Gw" "-D__STDC_CONSTANT_MACROS" "-D__STDC_FORMAT_MACROS" "-D__STDC_LIMIT_MACROS" "-DPACKAGE_VERSION=\"22.2.0-devel\"" "-DPACKAGE_BUGREPORT=\"https://gitlab.freedesktop.org/mesa/mesa/-/issues\" " "-DHAVE_SWRAST" "-DHAVE_D3D12" "-DHAVE_ZINK" "-DVIDEO_CODEC_VC1DEC=0" "-DVIDEO_CODEC_H264DEC=0" "-DVIDEO_CODEC_H264ENC=0" "-DVIDEO_CODEC_H265DEC=0" "-DVIDEO_CODEC_H265ENC=0" "-DHAVE_WINDOWS_PLATFORM" "-DHAVE_SURFACELESS_PLATFORM" "-DUSE_ELF_TLS" "-DUSE_TLS_BEHIND_FUNCTIONS" "-DENABLE_ST_OMX_BELLAGIO=0" "-DENABLE_ST_OMX_TIZONIA=0" "-DEGL_NO_X11" "-D_WINDOWS" "-D_WIN32_WINNT=0x0A00" "-DWINVER=0x0A00" "-DPIPE_SUBSYSTEM_WINDOWS_USER" "-D_USE_MATH_DEFINES" "-DVC_EXTRALEAN" "-D_CRT_SECURE_NO_WARNINGS" "-D_CRT_SECURE_NO_DEPRECATE" "-D_SCL_SECURE_NO_WARNINGS" "-D_SCL_SECURE_NO_DEPRECATE" "-D_ALLOW_KEYWORD_MACROS" "-D_HAS_EXCEPTIONS=0" "-DNOMINMAX" "-DMISSING_64BIT_ATOMICS" "-DHAVE_STRTOF" "-DHAVE_TIMESPEC_GET" "-DHAVE_QSORT_S" "-DHAVE_STRUCT_TIMESPEC" "-DHAVE_ZLIB" "-DHAVE_COMPRESSION" "-DLLVM_AVAILABLE" "-DMESA_LLVM_VERSION_STRING=\"12.0.1\"" "-DLLVM_IS_SHARED=0" "-DDRAW_LLVM_AVAILABLE" "-DMESA_EXECMEM" "-DVK_USE_PLATFORM_WIN32_KHR" "/wd4018" "/wd4056" "/wd4244" "/wd4267" "/wd4305" "/wd4351" "/wd4756" "/wd4800" "/wd4996" "/wd4291" "/wd4146" "/wd4200" "/wd4624" "/wd4309" "/wd4838" "/wd5105" "/we4020" "/we4024" "/Zc:__cplusplus" "-DADDR_FASTCALL=" "/Fdsrc\amd\common\libamd_common.a.p\ac_nir_opt_outputs.c.pdb" /Fosrc/amd/common/libamd_common.a.p/ac_nir_opt_outputs.c.obj "/c" ../mesa/src/amd/common/ac_nir_opt_outputs.c ../mesa/src/amd/common/ac_nir_opt_outputs.c(256): error C2059: syntax error: '}' [23/987] Compiling C object src/compiler/nir/libnir.a.p/nir_opt_preamble.c.obj ``` Signed-off-by:
Jesse Natalie <jenatali@microsoft.com> Reviewed-by:
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Fixes: 5d9ef0ef ("radv: Add the fuchsia radix sort") ../mesa/src/amd/vulkan/radix_sort/radv_radix_sort.c(148): error C2220: the following warning is treated as an error ../mesa/src/amd/vulkan/radix_sort/radv_radix_sort.c(148): warning C4098: 'vkDestroyPipeline': 'void' function returning a value [82/1129] Compiling C++ object src/amd/compiler/libaco.a.p/aco_instruction_selection.cpp.obj Signed-off-by:
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Fixes: 3269d34b ("llvmpipe/fence: make the fence id counter atomic") Fixes: ``` ../mesa/src/gallium/drivers/llvmpipe/lp_fence.c ../mesa/src/gallium/drivers/llvmpipe/lp_fence.c(47): error C2143: syntax error: missing ';' before 'type' ``` fence_id initialized to 0 Signed-off-by:
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There's no unistd.h on Windows, let's not include it unconditionally. But we also don't want to deal with DRM modifiers or DMABUFs on Windows, so let's also ifdef out the rest of that stuff. Fixes: a8b009ae ("vulkan/wsi: fix missing unistd include") Fixes: c72ff19a ("vulkan/wsi: Close file descriptors in wsi_destroy_image") Reviewed-By:
Boris Brezillon <boris.brezillon@collabora.com> Part-of: <mesa/mesa!16373>
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The single caller of this function (in st_glsl_to_ir.cpp) always passes false, so this is dead code. v2: Delete convert_vec_index_to_cond_assign method because all the callers are deleted too. Reviewed-by:
Matt Turner <mattst88@gmail.com> Part-of: <!16440>
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Tiger Lake and Ice Lake had similar results. (Ice Lake shown) total cycles in shared programs: 861153442 -> 861153533 (<.01%) cycles in affected programs: 14748 -> 14839 (0.62%) helped: 5 HURT: 10 helped stats (abs) min: 1 max: 2 x̄: 1.80 x̃: 2 helped stats (rel) min: 0.09% max: 0.18% x̄: 0.16% x̃: 0.17% HURT stats (abs) min: 2 max: 18 x̄: 10.00 x̃: 10 HURT stats (rel) min: 0.17% max: 1.54% x̄: 1.06% x̃: 1.24% 95% mean confidence interval for cycles value: 1.15 10.99 95% mean confidence interval for cycles %-change: 0.25% 1.07% Cycles are HURT. Skylake and Broadwell had similar results. (Skylake shown) total cycles in shared programs: 844405063 -> 844405073 (<.01%) cycles in affected programs: 1710 -> 1720 (0.58%) helped: 0 HURT: 4 HURT stats (abs) min: 2 max: 4 x̄: 2.50 x̃: 2 HURT stats (rel) min: 0.35% max: 1.16% x̄: 0.88% x̃: 1.00% 95% mean confidence interval for cycles value: 0.91 4.09 95% mean confidence interval for cycles %-change: 0.30% 1.45% Cycles are HURT. Haswell and all earlier Intel GPUs had similar results. (Haswell shown) total instructions in shared programs: 16710016 -> 16709769 (<.01%) instructions in affected programs: 5842 -> 5595 (-4.23%) helped: 64 HURT: 0 helped stats (abs) min: 3 max: 4 x̄: 3.86 x̃: 4 helped stats (rel) min: 3.36% max: 7.69% x̄: 4.52% x̃: 4.17% 95% mean confidence interval for instructions value: -3.95 -3.77 95% mean confidence interval for instructions %-change: -4.83% -4.22% Instructions are helped. total cycles in shared programs: 881088472 -> 881086722 (<.01%) cycles in affected programs: 68696 -> 66946 (-2.55%) helped: 58 HURT: 6 helped stats (abs) min: 10 max: 202 x̄: 36.41 x̃: 18 helped stats (rel) min: 0.81% max: 16.42% x̄: 4.15% x̃: 1.51% HURT stats (abs) min: 2 max: 88 x̄: 60.33 x̃: 68 HURT stats (rel) min: 0.17% max: 7.06% x̄: 4.94% x̃: 5.60% 95% mean confidence interval for cycles value: -42.14 -12.54 95% mean confidence interval for cycles %-change: -4.66% -1.94% Cycles are helped. No fossil-db changes on any Intel platform. Reviewed-by:
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As of ca63a5ed ("glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx"), this lowering pass does two things. It converts ir_binop_vector_extract to an if-ladder to select the dynamically indexed component, and it extracts a ir_binop_vector_extract from the source of an interpolateAt function and applies to the result instead. This change adds a flag to disable the former behavior. The latter is still useful, but NIR has better (and soon even better) ways of doing the former. Reviewed-by:
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This was originally part of a series that made other changes to this file, but all of those changes got dropped. Since the typing was already done, there's no reason to not fix the formatting. Reviewed-by:
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v2: Don't lower ffloor@64 to ffract@64 when both ops are to be lowered. Settle on ffloor in opt_algebraic because in can be lowered to other ops in lower_double_ops. Signed-off-by:Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>(v1) Jason Ekstrand <jason.ekstrand@collabora.com> (v1) Reviewed-by: Emma Anholt <emma@anholt.net> (v1) Part-of: <!16431>
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This is simpler and also avoids an assert() when the last block is empty. Fixes: e3a45a47 ("glsl: implement lower_packed_varyings() as a NIR pass") Acked-by:
Marek Olšák <marek.olsak@amd.com> Part-of: <!16527>
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Timur Kristóf authoredI forgot to use task_ring_offsets instead of ring_offsets when I ported this code to the new ABI. Fixes: a8bdcf3c Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com>
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Rhys Perry <pendingchaos02@gmail.com>
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Timur Kristóf authored
This is in the wrong place thanks to a rebase mistake. Fixes: 101a7321 Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
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Marek Olšák authored
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Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <mesa/mesa!16466>
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Marek Olšák authored
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Marek Olšák authored
When shader_query_buffers is NULL, the code treated as as non-empty. Fixes: 792a638b "radeonsi/gfx10: implement streamout-related queries" Reviewed-by:
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Marek Olšák authored
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Marek Olšák authored
It forces the best placement (usually VRAM) and evictions discard the contents instead of copying. Reviewed-by:
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Marek Olšák authored
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Marek Olšák authored
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Marek Olšák authored
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Marek Olšák authored
so that we don't need custom code for encrypted allocations Reviewed-by:
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Marek Olšák authored
It was getting difficult to add more heaps. This adds more heaps because more flag combinations are legal now. Invalid flag combinations are also handled better. Reviewed-by:
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Marek Olšák authored
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It has been disabled in December 2021 due to unreliability, and never got re-enabled. VEGA10 is disabled because it currently fails: Replay of parallel-rdp/uber_subgroup.foz failed Fossilize ERROR: Compute pipeline crashed or hung, hash: 520406f40241abf8. Rerun with: --compute-pipeline-range 4 5. Suggested-by:Martin Roukala (né Peres) <martin.roukala@mupuf.org> Reviewed-by:
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The primitive ID is required to be exported by the GS stage, so this should only be needed for NGG VS or TES without a GS stage. Otherwise, it's exported twice. No fossils-db changes. Signed-off-by:
Timur Kristóf <timur.kristof@gmail.com>
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We can have an empty dzn_cmd_buffer_query_pool_state::collect bitset, handle that case properly. Reviewed-by:
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It no longer exists. Signed-off-by:
Rhys Perry <pendingchaos02@gmail.com>
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It makes no sense to add the active heaps to the free heaps, just to remove them again. Instead, let's move them from the one list to the other. This fixes a crash in Doom 2016 after a while, due to resource exhaustion. Reviewed-by:
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Also document additional piglit failures and crashes with new tests. Multiple changes, mostly notable: - few new tests - traces downloader improvements Reviewed-by:
Emma Anholt <emma@anholt.net> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com>
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This allows glamor to successfully compile its shaders on the GC400. When running glamor using the GC400, Xorg reports that the compiled shaders exceed the maximum allowed instructions because the value reported from the kernel is halved. Xserver[314]: etna_draw_vbo:318: compiled shaders are not okay $ cat /sys/kernel/debug/dri/128/gpu | grep instruction_count instruction_count: 256 However, the spec for the Unified vertex-fragment shader explicitly lists 256 as the maximum number of instructions for each shader ("256 for vertex shaders; 256 for fragment shaders"). Signed-off-by:Kyle Russell <bkylerussell@gmail.com> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <!16383>
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Here as well as calling the pass we need to switch the order of some of the information gathering and optimisation calls. We also need to create a custom callback for the dead variables removal pass to clean up dead builtin varying in SSO programs without causing piglit regressions. shader-db results IRIS (BDW): total instructions in shared programs: 17487900 -> 17477072 (-0.06%) instructions in affected programs: 128682 -> 117854 (-8.41%) helped: 587 HURT: 82 helped stats (abs) min: 1 max: 145 x̄: 18.82 x̃: 20 helped stats (rel) min: 0.21% max: 77.78% x̄: 17.41% x̃: 8.85% HURT stats (abs) min: 1 max: 6 x̄: 2.68 x̃: 2 HURT stats (rel) min: 0.25% max: 9.76% x̄: 2.94% x̃: 2.16% 95% mean confidence interval for instructions value: -17.71 -14.66 95% mean confidence interval for instructions %-change: -16.40% -13.42% Instructions are helped. total cycles in shared programs: 857442520 -> 857170199 (-0.03%) cycles in affected programs: 112252720 -> 111980399 (-0.24%) helped: 13733 HURT: 13349 helped stats (abs) min: 1 max: 7293 x̄: 81.44 x̃: 10 helped stats (rel) min: <.01% max: 90.32% x̄: 3.30% x̃: 0.62% HURT stats (abs) min: 1 max: 7424 x̄: 63.38 x̃: 8 HURT stats (rel) min: <.01% max: 192.23% x̄: 3.28% x̃: 0.54% 95% mean confidence interval for cycles value: -14.01 -6.10 95% mean confidence interval for cycles %-change: -0.17% 0.06% Inconclusive result (%-change mean confidence interval includes 0). total sends in shared programs: 971443 -> 970010 (-0.15%) sends in affected programs: 4596 -> 3163 (-31.18%) helped: 446 HURT: 39 helped stats (abs) min: 1 max: 6 x̄: 3.40 x̃: 4 helped stats (rel) min: 3.03% max: 85.71% x̄: 46.48% x̃: 50.00% HURT stats (abs) min: 1 max: 3 x̄: 2.15 x̃: 2 HURT stats (rel) min: 6.67% max: 25.00% x̄: 15.16% x̃: 10.53% 95% mean confidence interval for sends value: -3.13 -2.78 95% mean confidence interval for sends %-change: -44.16% -38.88% Sends are helped. LOST: 235 GAINED: 262 Shader-db results radeonsi (RX580): 169505 shaders in 102144 tests Totals: SGPRS: 7698832 -> 7696552 (-0.03 %) VGPRS: 5547296 -> 5545280 (-0.04 %) Spilled SGPRs: 14795 -> 14773 (-0.15 %) Spilled VGPRs: 3782 -> 3782 (0.00 %) Private memory VGPRs: 1152 -> 1152 (0.00 %) Scratch size: 3872 -> 3872 (0.00 %) dwords per thread Code Size: 162946528 -> 162895264 (-0.03 %) bytes Max Waves: 2449334 -> 2449736 (0.02 %) Totals from affected shaders: SGPRS: 215024 -> 212744 (-1.06 %) VGPRS: 151976 -> 149960 (-1.33 %) Spilled SGPRs: 162 -> 140 (-13.58 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 5249916 -> 5198652 (-0.98 %) bytes Max Waves: 54588 -> 54990 (0.74 %) Panfrost trace checksum is updated as per discussion in: #6343 Some virpipe tess shader piglit tests are added as failures to CI these failures are not a regression but an uncovered existing bug exposed due to the linker no longer sorting internally facing shader interfaces in alphabetical order. See details in: #6481 Acked-by:
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This just converts the GLSL IR pass to NIR. Acked-by:
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And also call it via the NIR varying linker. Acked-by:
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With a NIR based linker we get better xfb packing, and we no longer depend on the GLSL IR optimisations to be able to link shaders with a large amount of dead input/outputs. Acked-by:
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This is essentially the old GLSL IR packing pass rewritten as a NIR based pass. Doing this packing in NIR after we have preformed NIRs optimisation passes can give us better packing results. Acked-by:
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