1. 22 Jun, 2020 1 commit
    • Neil Roberts's avatar
      gallium: Add pipe cap for primitive restart with fixed index · bb5fc901
      Neil Roberts authored
      Adds PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX which is a subset of the
      primitive restart cap for when the hardware can only support the fixed
      indices specified in GLES.
      
      The switch statements were automatically modified with this command:
      
      find \( \( -name \*.cpp -o -name \*.c \) \! -type l \) \
       -exec sed -i -r \
       's/^(\s*case\s+PIPE_CAP_PRIMITIVE_RESTART)\s*:.*$/\0\n\1_FIXED_INDEX:/' \
       {} \;
      
      v2: Add a note in screen.rst
      
      Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
      Reviewed by: Erik Faye-Lund <erik.faye-lund@collabora.com>
      
      Part-of: <!5559>
      bb5fc901
  2. 02 Jun, 2020 1 commit
  3. 21 Jan, 2020 1 commit
  4. 14 Nov, 2019 1 commit
  5. 10 Oct, 2019 1 commit
  6. 23 Jul, 2019 1 commit
  7. 10 Jul, 2019 1 commit
    • Erik Faye-Lund 's avatar
      gallium: get rid of PIPE_CAP_SM3 · 39e7fbf2
      Erik Faye-Lund authored
      PIPE_CAP_SM3 has always been an odd one out of all our caps. While most
      other caps are fine-grained and single-purpose, this cap encode several
      features in one. And since OpenGL cares more about single features, it'd
      be nice to get rid of this one.
      
      As it turns, this is now relatively simple. We only really care about
      three features using this cap, and those already got their own caps. So
      we can remove it, and make sure all current drivers just give the same
      response to all of them.
      
      The only place we *really* care about SM3 is in nine, and there we can
      instead just re-construct the information based on the finer-grained
      caps. This avoids DX9 semantics from needlessly leaking into all of the
      drivers, most of who doesn't care a whole lot about DX9 specifically.
      Signed-off-by: Erik Faye-Lund 's avatarErik Faye-Lund <erik.faye-lund@collabora.com>
      Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
      Acked-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
      39e7fbf2
  8. 12 Jun, 2019 1 commit
  9. 23 May, 2019 1 commit
    • Kenneth Graunke's avatar
      gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH count · a2d78344
      Kenneth Graunke authored
      TGSI's FBFETCH instruction currently only supports reading from a single
      render target, but NIR intrinsics can support multiple render targets.
      
      radeonsi can only support fetching from RT 0, but other drivers may be
      able to support fetching from any render target.
      
      To express this, this patch renames PIPE_CAP_TGSI_FS_FBFETCH to simply
      PIPE_CAP_FBFETCH, and converts it from a boolean "is FBFETCH supported?"
      to an integer number of render targets which can be fetched.
      Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
      a2d78344
  10. 13 May, 2019 1 commit
  11. 24 Apr, 2019 2 commits
  12. 08 Feb, 2019 1 commit
  13. 20 Sep, 2018 1 commit
  14. 07 Sep, 2018 2 commits
  15. 04 Sep, 2018 1 commit
    • Eric Anholt's avatar
      gallium: Add a helper for implementing PIPE_CAP_* default values. · ad782a70
      Eric Anholt authored
      One of the pains of implementing a gallium driver is filling in a million
      pipe caps you don't know about yet when you're just starting out.  One of
      the pains of working on gallium is copy-and-pasting your new PIPE_CAP into
      each driver.  We can fix both of these by having each driver call into the
      default helper from their default case, so that both sides can ignore each
      other until they need to.
      
      v2: fix i915g build, revert swr change to avoid breaking scons build
          (https://travis-ci.org/anholt/mesa/jobs/419739857)
      v3: Rebase on 3 new gallium caps.
      
      Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
      Cc: Bruce Cherniak <bruce.cherniak@intel.com>
      Cc: George Kyriazis <george.kyriazis@intel.com>
      Cc: Kenneth Graunke <kenneth@whitecape.org>
      ad782a70
  16. 25 Aug, 2018 1 commit
    • Kenneth Graunke's avatar
      gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE. · 12816088
      Kenneth Graunke authored
      Some hardware can do PIPE_TEX_WRAP_MIRROR_REPEAT but not
      PIPE_TEX_WRAP_MIRROR_CLAMP and PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER.
      
      Drivers for such hardware would like to advertise support for
      ARB_texture_mirror_clamp_to_edge but not EXT_texture_mirror_clamp.
      
      This commit adds a new PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE bit,
      changes the extension enable to be based on that, and enables it
      in all upstream drivers which supported PIPE_CAP_TEXTURE_MIRROR_CLAMP
      (so they continue supporting this mode).
      12816088
  17. 23 Aug, 2018 2 commits
  18. 31 Jul, 2018 2 commits
  19. 29 Jun, 2018 1 commit
  20. 15 Jun, 2018 1 commit
  21. 30 May, 2018 1 commit
  22. 01 May, 2018 1 commit
  23. 20 Mar, 2018 1 commit
  24. 17 Feb, 2018 1 commit
  25. 13 Feb, 2018 1 commit
  26. 30 Jan, 2018 1 commit
  27. 17 Jan, 2018 3 commits
  28. 19 Dec, 2017 1 commit
  29. 17 Nov, 2017 1 commit
  30. 09 Nov, 2017 2 commits
  31. 06 Nov, 2017 1 commit
  32. 01 Nov, 2017 1 commit
  33. 10 Oct, 2017 1 commit
    • Eric Anholt's avatar
      gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4. · ac0051a5
      Eric Anholt authored
      Because vc4 can control the order that tiles are rasterized in, we can use
      it to implement overlapping blits using normal drawing and
      GL_ARB_texture_barrier, as long as we can tell the kernel what order to
      render the tiles in.
      
      This commit introduces the core gallium support, vc4 changes will follow.
      
      v2: Fix on the simulator.
      v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
      v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
      v5: Drop vc4 changes from this commit, for clarity.
      
      Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
      ac0051a5