- 23 Oct, 2020 40 commits
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Alyssa Rosenzweig authored
Will use for Bifrost as well. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
So we have stack memory allocated. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Now that all the helpers are in place, we can wire it up. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
LOAD is the same as LOAD_UNIFORM (same instruction, I need to deduplicate the IR), STORE is basically the same as LOAD. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
We'll reuse the logic in spilling. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Given a node to spill, insert the appropriate loads and stores to spill it. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Clauses with exactly one instruction (not canonical terminology to my knowledge, but the notation is suggestive). Since these are isomorphic to the instructions themselves, we want helpers to go between the forms. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Ported from Midgard. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Likewise generates LOAD from tls. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Generates STORE to TLS. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
For future shader-db integration. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Simplified from Midgard. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Will be used to prevent double spills. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Like Midgard. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Streamline the logic and the bug goes away. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
We don't support 64-bit clauses and don't intend to (v6 only, v7 doesn't support them) so this is irrelevant. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Use idiomatic iterator. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Let's reuse the same routines across Midgard/Bifrost so we get proper handling of spilling. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
It makes it easier to read and will allow re-using common bits for the bifrost reload logic. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
We want to be able to pass a payload allocated from the pool, so let's change the function prototype to allow that. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Alyssa Rosenzweig authored
Now that panfrost_transfer is renamed to panfrost_ptr. Signed-off-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
And use it in panfrost_bo to store a GPU/CPU pointer tuple. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Now that the compiler has been patched to support all the instructions used by blit shaders we can compile them unconditionally. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Letting the caller zero-initialize the program object is error prone, not to mention that resources attached to the program might not be freed by the caller. Let's simplify that by letting the compiler allocate the panfrost_program object. Those objects should be freed with ralloc_free(). Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
We currently don't support txf_ms instructions specifying a texel offset src. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
No need to add a COMBINE instruction if TEXC only needs zero or one staging reg. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Sample ID is preloaded in r61. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
index can have both a SPECIAL flag and PAN_IS_REG (bit 0) set, but we shouln't treat the index as a register in that case. Let's bail out early in bi_print_dest_index() when we're passed a special index that's not a register. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
It's just easier to identify the different layouts this way. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
The internal state is updated every time a tiler job is executed, and pandecode complains that unused bits are not zero-ed when that happens. Define the internal state (not meant to be set by the driver) to remove those spurious errors. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
When injecting a tiler job, we shouln't make it depend on the last tiler job, but instead make the first tiler job depend on it. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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Boris Brezillon authored
Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <!7206>
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