 06 Aug, 2018 11 commits


Eric Anholt authored
VC5 isn't a useful name any more, just stick to v3d.

Eric Anholt authored
Fixes bad rendering when forcing 2 spills in glxgears. Cc: "18.2" <mesastable@lists.freedesktop.org>

Eric Anholt authored
Found when debugging register spilling  we would try to spill the dest of a STVPMV, inserting spill code after entering the last segment. In fact, we were likely to to choose to do this, given that the STVPMV "dest" temp was never read from, making it cheap to spill. Cc: "18.2" <mesastable@lists.freedesktop.org>

Eric Anholt authored
The simulator complained that we had write responses outstanding at shader end. It seems that a TMU read does not guarantee that previous TMU writes by the thread have completed, which surprised me. Cc: "18.2" <mesastable@lists.freedesktop.org>

Eric Anholt authored
Found while forcing some spilling, which creates a lot of short tmua>thrsw>ldtmu sequences. Cc: "18.2" <mesastable@lists.freedesktop.org>

Eric Anholt authored
This is useful for periodically testing out register spilling to see how it goes on simple shaders, rather than only failing on insanely complicated ones.

chadversary authored
In commit cf54bd5e, dri_sw_winsys.c began using <sys/shm.h> to support the new functions putImageShm, getImageShm in DRI_SWRastLoader. But Android began supporting System V shared memory only in Oreo. Nougat has no shm headers. Fix the build by ifdef'ing out the shm code on Nougat. Fixes: cf54bd5e "drisw: use shared memory when possible" Reviewedby: Dave Airlie <airlied@redhat.com> Cc: MarcAndré Lureau <marcandre.lureau@gmail.com>

Ian Romanick authored
Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107483 Fixes: 3d6900d7 ("glapi: define AMD_framebuffer_multisample_advanced and add its functions") Reviewedby: Marek Olšák <marek.olsak@amd.com> Cc: Vinson Lee <vlee@freedesktop.org>

Ian Romanick authored
The GL_AMD_framebuffer_multisample_advanced spec says: OpenGL ES dependencies: Requires OpenGL ES 3.0. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107483 Fixes: 3d6900d7 ("glapi: define AMD_framebuffer_multisample_advanced and add its functions") Reviewedby: Marek Olšák <marek.olsak@amd.com> Cc: Vinson Lee <vlee@freedesktop.org>

Gert Wollny authored
os.path.exists doesn't return True for stale symlinks, but they are in the way later, when a link/file with the same name is to be created. For instance it is conceivable that the pointed to file is replaced by a file with a new name, and then the symlink is dead. To handle this check specifically for all existing symlinks to be removed. (This bugged me for some time with a link libXvMCr600.so always being in the way of installing this file) v2: use only os.lexist and replace all instances of os.exist (Dylan Baker) v3: handle directory check correctly (Eric Engestrom) Fixes: f7f1b30f ("meson: extend install_megadrivers script to handle symmlinking") Reviewedby: Eric Engestrom <eric.engestrom@intel.com>(v2 minus dir check) Reviewedby: Dylan Baker <dylan@pnwbakers.com> Signedoffby: Gert Wollny <gert.wollny@collabora.com>

Tapani Pälli authored
This change helps with some of the dEQPVK.wsi.android.* tests that try to create swapchain with using such formats. Signedoffby: Tapani Pälli <tapani.palli@intel.com> Reviewedby: Chad Versace <chadversary@chromium.org>

 04 Aug, 2018 29 commits


Karol Herbst authored
We already guarded all OP_SULDP against out of bound accesses, but we ended up just reusing whatever value was stored in the dest registers. Fixes CTS test shader_image_load_store.incomplete_textures v2: fix for loads not ending up with predicates (bindless_texture) v3: fix replacing the def Cc: <mesastable@lists.freedesktop.org> Reviewedby: Ilia Mirkin <imirkin@alum.mit.edu> Signedoffby: Karol Herbst <kherbst@redhat.com>

Karol Herbst authored
mitigates hurt shaders after adding sqrt: total instructions in shared programs : 5456166 > 5454825 (0.02%) total gprs used in shared programs : 647522 > 647551 (0.00%) total shared used in shared programs : 389120 > 389120 (0.00%) total local used in shared programs : 21064 > 21064 (0.00%) total bytes used in shared programs : 58288696 > 58274448 (0.02%) local shared gpr inst bytes helped 0 0 0 516 516 hurt 0 0 27 2 2 Reviewedby: Ilia Mirkin <imirkin@alum.mit.edu> Signedoffby: Karol Herbst <kherbst@redhat.com>

Karol Herbst authored
./GpuTest /test=pixmark_piano 1024x640 30sec: 301 > 327 points shaderdb: total instructions in shared programs : 5472103 > 5456166 (0.29%) total gprs used in shared programs : 647530 > 647522 (0.00%) total shared used in shared programs : 389120 > 389120 (0.00%) total local used in shared programs : 21064 > 21064 (0.00%) total bytes used in shared programs : 58459304 > 58288696 (0.29%) local shared gpr inst bytes helped 0 0 27 8281 8281 hurt 0 0 21 431 431 v2: use NVISA_GM200_CHIPSET Reviewedby: Ilia Mirkin <imirkin@alum.mit.edu> Signedoffby: Karol Herbst <kherbst@redhat.com>

Lionel Landwerlin authored
Remove the if tools condition and just put it through the install: parameter. Signedoffby: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewedby: Eric Engestrom <eric.engestrom@intel.com>

Lionel Landwerlin authored
Since we don't support streaming an aub file, we can drop the decoding status enum. v2: include stdbool (Eric) Signedoffby: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewedby: Eric Engestrom <eric.engestrom@intel.com>

Lionel Landwerlin authored
Reviewedby: Eric Engestrom <eric.engestrom@intel.com>

Lionel Landwerlin authored
Signedoffby: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewedby: Eric Engestrom <eric.engestrom@intel.com>

Lionel Landwerlin authored
Signedoffby: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewedby: Eric Engestrom <eric.engestrom@intel.com>

Lionel Landwerlin authored
Up to now we've been lucky that the buffer returned was always exactly at the address we requested. Fixes: 144b40db ("intel: aubinator: drop the 1Tb GTT mapping") Signedoffby: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewedby: Rafael Antognolli <rafael.antognolli@intel.com>

Ian Romanick authored
All Gen7+ platforms had similar results. (Skylake shown) total instructions in shared programs: 14276886 > 14276838 (<.01%) instructions in affected programs: 312 > 264 (15.38%) helped: 2 HURT: 0 total cycles in shared programs: 532578395 > 532570985 (<.01%) cycles in affected programs: 682562 > 675152 (1.09%) helped: 374 HURT: 4 helped stats (abs) min: 2 max: 200 x̄: 20.39 x̃: 18 helped stats (rel) min: 0.07% max: 11.64% x̄: 1.25% x̃: 1.28% HURT stats (abs) min: 2 max: 114 x̄: 53.50 x̃: 49 HURT stats (rel) min: 0.06% max: 11.70% x̄: 5.02% x̃: 4.15% 95% mean confidence interval for cycles value: 21.30 17.91 95% mean confidence interval for cycles %change: 1.30% 1.06% Cycles are helped. Sandy Bridge total instructions in shared programs: 10488123 > 10488075 (<.01%) instructions in affected programs: 336 > 288 (14.29%) helped: 2 HURT: 0 total cycles in shared programs: 150260379 > 150260439 (<.01%) cycles in affected programs: 4726 > 4786 (1.27%) helped: 0 HURT: 2 No changes on Iron Lake or GM45. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen platforms had pretty similar results. (Skylake shown) total instructions in shared programs: 14276892 > 14276886 (<.01%) instructions in affected programs: 484 > 478 (1.24%) helped: 2 HURT: 0 total cycles in shared programs: 532578397 > 532578395 (<.01%) cycles in affected programs: 3522 > 3520 (0.06%) helped: 1 HURT: 0 Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen platforms had pretty similar results. (Skylake shown) total cycles in shared programs: 532578400 > 532578397 (<.01%) cycles in affected programs: 2784 > 2781 (0.11%) helped: 1 HURT: 1 helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4 helped stats (rel) min: 0.26% max: 0.26% x̄: 0.26% x̃: 0.26% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.08% max: 0.08% x̄: 0.08% x̃: 0.08% v2: s/fmax/fmin/. Noticed by Thomas Helland. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
No changes on any Gen platform. v2: s/fmax/fmin/. Noticed by Thomas Helland. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen6+ platforms had similar results. (Skylake shown) total instructions in shared programs: 14276961 > 14276892 (<.01%) instructions in affected programs: 3215 > 3146 (2.15%) helped: 28 HURT: 0 helped stats (abs) min: 1 max: 6 x̄: 2.46 x̃: 2 helped stats (rel) min: 0.47% max: 9.52% x̄: 4.34% x̃: 1.92% 95% mean confidence interval for instructions value: 2.87 2.06 95% mean confidence interval for instructions %change: 5.73% 2.95% Instructions are helped. total cycles in shared programs: 532577068 > 532578400 (<.01%) cycles in affected programs: 121864 > 123196 (1.09%) helped: 35 HURT: 30 helped stats (abs) min: 2 max: 268 x̄: 42.34 x̃: 22 helped stats (rel) min: 0.12% max: 12.14% x̄: 3.22% x̃: 1.86% HURT stats (abs) min: 2 max: 246 x̄: 93.80 x̃: 36 HURT stats (rel) min: 0.09% max: 13.63% x̄: 4.47% x̃: 2.58% 95% mean confidence interval for cycles value: 5.02 46.01 95% mean confidence interval for cycles %change: 0.99% 1.65% Inconclusive result (value mean confidence interval includes 0). Iron Lake and GM45 had similar results. (Iron Lake shown) total instructions in shared programs: 7781299 > 7781342 (<.01%) instructions in affected programs: 22300 > 22343 (0.19%) helped: 13 HURT: 40 helped stats (abs) min: 2 max: 3 x̄: 2.85 x̃: 3 helped stats (rel) min: 1.15% max: 7.69% x̄: 3.72% x̃: 3.33% HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.26% max: 1.30% x̄: 0.47% x̃: 0.43% 95% mean confidence interval for instructions value: 0.23 1.39 95% mean confidence interval for instructions %change: 1.18% 0.07% Inconclusive result (%change mean confidence interval includes 0). total cycles in shared programs: 177878928 > 177879332 (<.01%) cycles in affected programs: 383298 > 383702 (0.11%) helped: 7 HURT: 43 helped stats (abs) min: 2 max: 18 x̄: 10.00 x̃: 10 helped stats (rel) min: 0.17% max: 4.81% x̄: 2.62% x̃: 3.40% HURT stats (abs) min: 2 max: 38 x̄: 11.02 x̃: 12 HURT stats (rel) min: 0.08% max: 1.54% x̄: 0.25% x̃: 0.09% 95% mean confidence interval for cycles value: 5.21 10.95 95% mean confidence interval for cycles %change: 0.51% 0.21% Inconclusive result (%change mean confidence interval includes 0). v2: s/fmin/fmax/. Noticed by Thomas Helland. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen platforms had pretty similar results. (Skylake shown) total instructions in shared programs: 14276964 > 14276961 (<.01%) instructions in affected programs: 411 > 408 (0.73%) helped: 3 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.47% max: 1.96% x̄: 1.04% x̃: 0.68% total cycles in shared programs: 532577062 > 532577068 (<.01%) cycles in affected programs: 1093 > 1099 (0.55%) helped: 1 HURT: 1 helped stats (abs) min: 16 max: 16 x̄: 16.00 x̃: 16 helped stats (rel) min: 7.77% max: 7.77% x̄: 7.77% x̃: 7.77% HURT stats (abs) min: 22 max: 22 x̄: 22.00 x̃: 22 HURT stats (rel) min: 2.48% max: 2.48% x̄: 2.48% x̃: 2.48% Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen6+ platforms had pretty similar results. (Skylake shown) total instructions in shared programs: 14277184 > 14276964 (<.01%) instructions in affected programs: 10082 > 9862 (2.18%) helped: 37 HURT: 1 helped stats (abs) min: 1 max: 30 x̄: 5.97 x̃: 4 helped stats (rel) min: 0.14% max: 16.00% x̄: 5.23% x̃: 2.04% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.70% max: 0.70% x̄: 0.70% x̃: 0.70% 95% mean confidence interval for instructions value: 7.87 3.71 95% mean confidence interval for instructions %change: 6.98% 3.16% Instructions are helped. total cycles in shared programs: 532577990 > 532577062 (<.01%) cycles in affected programs: 170959 > 170031 (0.54%) helped: 33 HURT: 9 helped stats (abs) min: 2 max: 120 x̄: 30.91 x̃: 30 helped stats (rel) min: 0.02% max: 7.65% x̄: 2.66% x̃: 1.13% HURT stats (abs) min: 2 max: 24 x̄: 10.22 x̃: 8 HURT stats (rel) min: 0.09% max: 1.79% x̄: 0.61% x̃: 0.22% 95% mean confidence interval for cycles value: 31.23 12.96 95% mean confidence interval for cycles %change: 2.90% 1.02% Cycles are helped. Iron Lake and GM45 had similar results. (Iron Lake shown) total instructions in shared programs: 7781539 > 7781301 (<.01%) instructions in affected programs: 10169 > 9931 (2.34%) helped: 32 HURT: 0 helped stats (abs) min: 2 max: 20 x̄: 7.44 x̃: 6 helped stats (rel) min: 0.47% max: 17.02% x̄: 4.03% x̃: 1.88% 95% mean confidence interval for instructions value: 9.53 5.34 95% mean confidence interval for instructions %change: 5.94% 2.12% Instructions are helped. total cycles in shared programs: 177878590 > 177878932 (<.01%) cycles in affected programs: 78706 > 79048 (0.43%) helped: 7 HURT: 21 helped stats (abs) min: 6 max: 34 x̄: 24.57 x̃: 28 helped stats (rel) min: 0.15% max: 8.33% x̄: 4.66% x̃: 6.37% HURT stats (abs) min: 2 max: 86 x̄: 24.48 x̃: 22 HURT stats (rel) min: 0.01% max: 4.28% x̄: 1.21% x̃: 0.70% 95% mean confidence interval for cycles value: 0.30 24.13 95% mean confidence interval for cycles %change: 1.52% 1.01% Inconclusive result (%change mean confidence interval includes 0). v2: s/fmin/fmax/. Noticed by Thomas Helland. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
Unlike the much older abs(a) >= 0.0 transformation, this is not precise. The behavior changes if a is NaN. All Gen platforms had pretty similar results. (Skylake shown) total instructions in shared programs: 14277216 > 14277184 (<.01%) instructions in affected programs: 2300 > 2268 (1.39%) helped: 8 HURT: 0 helped stats (abs) min: 1 max: 8 x̄: 4.00 x̃: 3 helped stats (rel) min: 0.48% max: 15.15% x̄: 4.41% x̃: 1.01% 95% mean confidence interval for instructions value: 6.45 1.55 95% mean confidence interval for instructions %change: 9.96% 1.13% Inconclusive result (%change mean confidence interval includes 0). total cycles in shared programs: 532577848 > 532577990 (<.01%) cycles in affected programs: 17486 > 17628 (0.81%) helped: 2 HURT: 5 helped stats (abs) min: 2 max: 6 x̄: 4.00 x̃: 4 helped stats (rel) min: 0.06% max: 1.81% x̄: 0.93% x̃: 0.93% HURT stats (abs) min: 6 max: 50 x̄: 30.00 x̃: 26 HURT stats (rel) min: 0.55% max: 2.17% x̄: 1.19% x̃: 1.02% 95% mean confidence interval for cycles value: 1.06 41.63 95% mean confidence interval for cycles %change: 0.58% 1.74% Inconclusive result (value mean confidence interval includes 0). Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen platforms had pretty similar results. (Skylake shown) total instructions in shared programs: 14277220 > 14277216 (<.01%) instructions in affected programs: 422 > 418 (0.95%) helped: 2 HURT: 0 total cycles in shared programs: 532577908 > 532577848 (<.01%) cycles in affected programs: 2800 > 2740 (2.14%) helped: 2 HURT: 0 Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
All Gen platforms had pretty similar results. (Skylake shown) total instructions in shared programs: 14277230 > 14277220 (<.01%) instructions in affected programs: 751 > 741 (1.33%) helped: 4 HURT: 0 helped stats (abs) min: 2 max: 3 x̄: 2.50 x̃: 2 helped stats (rel) min: 1.23% max: 1.40% x̄: 1.32% x̃: 1.32% 95% mean confidence interval for instructions value: 3.42 1.58 95% mean confidence interval for instructions %change: 1.47% 1.17% Instructions are helped. total cycles in shared programs: 532577947 > 532577908 (<.01%) cycles in affected programs: 10641 > 10602 (0.37%) helped: 4 HURT: 3 helped stats (abs) min: 1 max: 40 x̄: 13.75 x̃: 7 helped stats (rel) min: 0.11% max: 3.08% x̄: 1.10% x̃: 0.60% HURT stats (abs) min: 2 max: 8 x̄: 5.33 x̃: 6 HURT stats (rel) min: 0.13% max: 0.55% x̄: 0.30% x̃: 0.23% 95% mean confidence interval for cycles value: 20.69 9.55 95% mean confidence interval for cycles %change: 1.63% 0.63% Inconclusive result (value mean confidence interval includes 0). Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com> Reviewedby: Jason Ekstrand <jason@jlekstrand.net>

Ian Romanick authored
Broadwell and Skylake had similar results. (Skylake shown) total instructions in shared programs: 14277620 > 14277230 (<.01%) instructions in affected programs: 36905 > 36515 (1.06%) helped: 101 HURT: 6 helped stats (abs) min: 1 max: 6 x̄: 4.46 x̃: 6 helped stats (rel) min: 0.32% max: 7.69% x̄: 1.80% x̃: 1.51% HURT stats (abs) min: 1 max: 28 x̄: 10.00 x̃: 1 HURT stats (rel) min: 0.33% max: 1.74% x̄: 0.68% x̃: 0.47% 95% mean confidence interval for instructions value: 4.59 2.70 95% mean confidence interval for instructions %change: 1.90% 1.41% Instructions are helped. total cycles in shared programs: 532580716 > 532577947 (<.01%) cycles in affected programs: 940575 > 937806 (0.29%) helped: 92 HURT: 12 helped stats (abs) min: 2 max: 158 x̄: 51.04 x̃: 62 helped stats (rel) min: 0.24% max: 3.99% x̄: 2.14% x̃: 2.41% HURT stats (abs) min: 10 max: 1112 x̄: 160.58 x̃: 63 HURT stats (rel) min: 0.06% max: 21.90% x̄: 4.22% x̃: 0.20% 95% mean confidence interval for cycles value: 50.66 2.59 95% mean confidence interval for cycles %change: 2.09% 0.73% Cycles are helped. total spills in shared programs: 8116 > 8124 (0.10%) spills in affected programs: 200 > 208 (4.00%) helped: 0 HURT: 2 total fills in shared programs: 11086 > 11094 (0.07%) fills in affected programs: 436 > 444 (1.83%) helped: 0 HURT: 2 Ivy Bridge and Haswell had similar results. (Haswell shown) total instructions in shared programs: 12979054 > 12978067 (<.01%) instructions in affected programs: 33633 > 32646 (2.93%) helped: 120 HURT: 2 helped stats (abs) min: 1 max: 13 x̄: 8.53 x̃: 13 helped stats (rel) min: 0.30% max: 16.67% x̄: 4.55% x̃: 3.17% HURT stats (abs) min: 18 max: 18 x̄: 18.00 x̃: 18 HURT stats (rel) min: 1.15% max: 2.84% x̄: 2.00% x̃: 2.00% 95% mean confidence interval for instructions value: 9.19 6.99 95% mean confidence interval for instructions %change: 5.27% 3.62% Instructions are helped. total cycles in shared programs: 411212880 > 411199636 (<.01%) cycles in affected programs: 696441 > 683197 (1.90%) helped: 107 HURT: 5 helped stats (abs) min: 2 max: 864 x̄: 124.90 x̃: 146 helped stats (rel) min: 0.03% max: 29.20% x̄: 8.58% x̃: 5.88% HURT stats (abs) min: 2 max: 50 x̄: 24.00 x̃: 22 HURT stats (rel) min: 0.01% max: 5.35% x̄: 1.29% x̃: 0.25% 95% mean confidence interval for cycles value: 136.96 99.54 95% mean confidence interval for cycles %change: 9.75% 6.53% Cycles are helped. total spills in shared programs: 78623 > 78631 (0.01%) spills in affected programs: 66 > 74 (12.12%) helped: 0 HURT: 2 total fills in shared programs: 80104 > 80108 (<.01%) fills in affected programs: 133 > 137 (3.01%) helped: 0 HURT: 2 No changes on Sandy Bridge, Iron Lake, or GM45. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
Broadwell and Skylake had similar results. (Skylake shown) total instructions in shared programs: 14277978 > 14277620 (<.01%) instructions in affected programs: 36957 > 36599 (0.97%) helped: 76 HURT: 1 helped stats (abs) min: 2 max: 90 x̄: 4.89 x̃: 4 helped stats (rel) min: 0.44% max: 5.88% x̄: 1.04% x̃: 0.87% HURT stats (abs) min: 14 max: 14 x̄: 14.00 x̃: 14 HURT stats (rel) min: 0.36% max: 0.36% x̄: 0.36% x̃: 0.36% 95% mean confidence interval for instructions value: 7.06 2.24 95% mean confidence interval for instructions %change: 1.28% 0.77% Instructions are helped. total cycles in shared programs: 532584581 > 532580716 (<.01%) cycles in affected programs: 973591 > 969726 (0.40%) helped: 76 HURT: 1 helped stats (abs) min: 2 max: 9940 x̄: 159.80 x̃: 32 helped stats (rel) min: <.01% max: 8.70% x̄: 1.15% x̃: 1.19% HURT stats (abs) min: 8280 max: 8280 x̄: 8280.00 x̃: 8280 HURT stats (rel) min: 2.10% max: 2.10% x̄: 2.10% x̃: 2.10% 95% mean confidence interval for cycles value: 386.98 286.59 95% mean confidence interval for cycles %change: 1.41% 0.81% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 8127 > 8116 (0.14%) spills in affected programs: 108 > 97 (10.19%) helped: 1 HURT: 0 total fills in shared programs: 11090 > 11086 (0.04%) fills in affected programs: 440 > 436 (0.91%) helped: 1 HURT: 1 Haswell total instructions in shared programs: 12979174 > 12979054 (<.01%) instructions in affected programs: 9040 > 8920 (1.33%) helped: 14 HURT: 1 helped stats (abs) min: 2 max: 34 x̄: 8.79 x̃: 6 helped stats (rel) min: 0.41% max: 7.04% x̄: 2.66% x̃: 1.14% HURT stats (abs) min: 3 max: 3 x̄: 3.00 x̃: 3 HURT stats (rel) min: 0.19% max: 0.19% x̄: 0.19% x̃: 0.19% 95% mean confidence interval for instructions value: 13.58 2.42 95% mean confidence interval for instructions %change: 3.94% 1.01% Instructions are helped. total cycles in shared programs: 411227148 > 411212880 (<.01%) cycles in affected programs: 630506 > 616238 (2.26%) helped: 15 HURT: 0 helped stats (abs) min: 2 max: 11192 x̄: 951.20 x̃: 38 helped stats (rel) min: <.01% max: 16.01% x̄: 3.92% x̃: 0.17% 95% mean confidence interval for cycles value: 2544.28 641.88 95% mean confidence interval for cycles %change: 6.89% 0.94% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 78626 > 78623 (<.01%) spills in affected programs: 42 > 39 (7.14%) helped: 1 HURT: 0 total fills in shared programs: 80111 > 80104 (<.01%) fills in affected programs: 140 > 133 (5.00%) helped: 1 HURT: 1 Ivy Bridge total instructions in shared programs: 11684101 > 11684030 (<.01%) instructions in affected programs: 3080 > 3009 (2.31%) helped: 4 HURT: 1 helped stats (abs) min: 5 max: 59 x̄: 18.50 x̃: 5 helped stats (rel) min: 6.47% max: 7.04% x̄: 6.87% x̃: 6.99% HURT stats (abs) min: 3 max: 3 x̄: 3.00 x̃: 3 HURT stats (rel) min: 0.15% max: 0.15% x̄: 0.15% x̃: 0.15% 95% mean confidence interval for instructions value: 45.59 17.19 95% mean confidence interval for instructions %change: 9.38% 1.56% Inconclusive result (value mean confidence interval includes 0). total cycles in shared programs: 258407697 > 258389653 (<.01%) cycles in affected programs: 328323 > 310279 (5.50%) helped: 5 HURT: 0 helped stats (abs) min: 32 max: 14908 x̄: 3608.80 x̃: 32 helped stats (rel) min: 1.26% max: 17.22% x̄: 9.30% x̃: 10.60% 95% mean confidence interval for cycles value: 11616.71 4399.11 95% mean confidence interval for cycles %change: 16.56% 2.03% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 4537 > 4528 (0.20%) spills in affected programs: 64 > 55 (14.06%) helped: 1 HURT: 0 total fills in shared programs: 4823 > 4815 (0.17%) fills in affected programs: 189 > 181 (4.23%) helped: 1 HURT: 1 Sandy Bridge total instructions in shared programs: 10488464 > 10488449 (<.01%) instructions in affected programs: 272 > 257 (5.51%) helped: 3 HURT: 0 helped stats (abs) min: 5 max: 5 x̄: 5.00 x̃: 5 helped stats (rel) min: 5.49% max: 5.56% x̄: 5.51% x̃: 5.49% total cycles in shared programs: 150263359 > 150263263 (<.01%) cycles in affected programs: 7978 > 7882 (1.20%) helped: 3 HURT: 0 helped stats (abs) min: 32 max: 32 x̄: 32.00 x̃: 32 helped stats (rel) min: 1.15% max: 1.23% x̄: 1.20% x̃: 1.23% No changes on Iron Lake or GM45. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Ian Romanick authored
Unlike the much older abs(a) >= 0.0 transformation, this is not precise. The behavior changes if the source is NaN. No shaderdb changes on any platform. Signedoffby: Ian Romanick <ian.d.romanick@intel.com> Reviewedby: Thomas Helland <thomashelland90@gmail.com>

Marek Olšák authored

Marek Olšák authored
Reviewedby: Brian Paul <brianp@vmware.com>

Marek Olšák authored
Reviewedby: Brian Paul <brianp@vmware.com>

Marek Olšák authored
Reviewedby: Brian Paul <brianp@vmware.com>

Marek Olšák authored
 relax FBO completeness rules  validate sample counts Reviewedby: Brian Paul <brianp@vmware.com>

Marek Olšák authored
Reviewedby: Brian Paul <brianp@vmware.com>

Marek Olšák authored
Reviewedby: Brian Paul <brianp@vmware.com>
