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This reverts commit 4fb2eddf.
This reverts commit 7a1deb16.
This reverts commit 2b6a1723.
This reverts commit 5af81393.
This reverts commit 87900afe.

A couple of problems were discovered after this series was merged that
cause breakage in different configurations:

   (1) It seems that using -mf16c also enables AVX, leading to SIGILL on
   platforms that do not support AVX.
   (2) Since clang only warns about unknown flags, and as I understand
   it Meson's handling in cc.has_argument() is broken, the F16C code is
   wrongly enabled when clang is used, even for example on ARM, leading
   to a compilation error.

Closes: #3583Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <!6969>

Android.mk and Makefile.sources are still defining virgl_driinfo.h target
This patch removes the remaining gen rules

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_virgl_intermediates/virgl/virgl_driinfo.h
...
cp: bad 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_virgl_intermediates/virgl/virgl_driinfo.h': No such file or directory

Fixes: 974981c4 ("gallium/drm: Make the pipe loader handle the driconf merging.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <!6880>

Android.mk and Makefile.sources are still defining si_driinfo.h target
This patch removes the remaining gen rules

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/radeonsi/si_driinfo.h
...
cp: bad 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/radeonsi/si_driinfo.h': No such file or directory

Fixes: 974981c4 ("gallium/drm: Make the pipe loader handle the driconf merging.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6880>

Android.mk and Makefile.sources are still defining iris_driinfo.h target
This patch removes the remaining gen rules

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/iris/iris_driinfo.h
...
cp: bad 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/iris/iris_driinfo.h': No such file or directory

Fixes: 974981c4 ("gallium/drm: Make the pipe loader handle the driconf merging.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!6880>

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <!6945>

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <!6945>

Note, the aligned versions aren't handled specially yet.

The float16buffer capability is now at least partially supported after
this patch, so move it to be supported when kernels are supported.

v2 (Jason Ekstrand):
 - A few cosmetic cleanups around type/base_type
 - Rebased on top of the big SPIR-V SSA value rework
 - Use the new version of the conversion helpers
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <!6945>

At that point in the function, we don't know if it's a load or a store
so calling it dest_type isn't really helpful.  Also, we don't really
want the glsl_type; we want the base_type.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <!6945>

This is done for kernels via the new convert_alu_types intrinsic.  For
Vulkan and OpenGL, we maintain the old path so that drivers don't have
to add that lowering pass.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <!6945>

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <!6945>

This adds primarily two passes:  One is a lowering pass which turns
these conversion intrinsics into a series of ALU ops.  The other is an
optimization pass which attempt to simplify the conversion whenever
possible in the hopes that we can turn it into a "normal" conversion op
which doesn't need special treatment.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <!6945>

Most of these were originally written by Daniel Stone in the Microsoft
ClOn12 branch, reworked by Jesse Natalie, fixed by Boris Brezillon, and
possibly touched by others along the way.  Unfortunately, none of that
is in the commit history thanks to living in the CLOn12 branch.

I ported them to mesa master and further reworked things for better
cosmetics.  In particular,

 1. They now live in a builder helper rather than in vtn_alu.c.

 2. Instead of looping inside each builder helper, we just trust NIR
    vector instructions to handle vectors.

 3. Lots of re-arranging of the helpers for clarity, better asserting,
    and better re-use with the upcoming lowering pass.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <!6945>

This new intrinsic is capable of handling the full range of conversions
from OpenCL including rounding modes and possible saturation.  The
intention is that we'll emit this intrinsic directly from spirv_to_nir
and then lower it to ALU ops later.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <!6945>

We're about to introduce conversion ops which are going to want two
different types.  We may as well just split the one we have rather than
end up with three.  There are a couple places where this is mildly
inconvenient but most of the time I find it to actually be nicer.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <mesa/mesa!6945>

fixes piglit cl get-global-id
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <!6954>

(can remove lavapipe setting this later).
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <!6954>

Make the driver only read values for the active lanes,
otherwise it can cause unwanted oob accesses that aren't
the apps fault.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <!6954>

Workaround # 22011374674
Applied to i965, iris and anv drivers
No performance impact is observed with WA.

Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6948>

The new place is where shader variants are generated.

This is a prerequisite for inlinable uniforms.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!6948>

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6948>

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6948>

Apps often enable only 1 plane for gl_ClipVertex, which means 1 scalar
clip distance.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6948>

Add a vertex count threshold into si_shader_selector to simplify
the draw_vbo code.

The new option is supposed to be used in 00-mesa-defaults.conf and should be
tweaked for best performance unlike the AMD_DEBUG experimental options.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6948>

We should set "Full Surface Depth and Stencil Clear" field of WM_HZ_OP
3DSTATE packet, only when application requires the entire depth surface
to be cleared.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <mesa/mesa!6549>

This gets rid of multiple HiZ ambiguate operations per frame in
Witcher 3.

v2:
- Fix typo (Tapani)
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <!6549>

This is a mostly cosmetic change but there is one subtle functional
issue:  If we ever render to a 3D depth image, we are now handling the
base layer and number of layers correctly.  I'm not sure rendering to 3D
depth is even allowed but we can theoretically handle it now.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <!6549>

Now that we're enabling HiZ on multi-layer images, there's no reason why
we can't enable HiZ clears for multi-view.  The only reason I can think
of why we didn't before was because no one thought to and the old code
didn't.  Enabling this means that an attachment will get HiZ cleared if
and only if att_state->fast_clear.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <!6549>

So far, the callback to create a resource from a memory object had code
for importing textures only. Modified it to allow importing buffers too.

Fixes the following piglit tests:
- ext_external_objects/vk-buf-exchange
- ext_external_objects/vk-pix-buf-update-errors
- ext_external_objects/vk-vert-buf-update-errors
- ext_external_objects/vk-vert-buf-reuse

v2: Used si_alloc_buffer_struct instead of CALLOC
v3: Fixed indentation issue, removed free in case of unsuccessful
allocation, joined two if conditions together
Signed-off-by: Eleni Maria Stea <estea@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!6364>

Lowering IO for VS, TCS, TES and GS still have to be done for LLVM.

No fossils-db change on NAVI10.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <!6897>

IO are now lowered before the shader info pass is called and the
output usage masks have to be gathered from store_output instead.

This is currently only used by ACO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <!6897>

NIR if statements only take one component, but TGSI registers are vec4.
We're supposed to compare the x component, per
https://docs.mesa3d.org/gallium/tgsi.html#opcode-IF.

Fixes: f103bded ("ttn: Use nir control flow insertion helpers")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Leo Liu <leo.liu@amd.com>
Closes: #3585
Part-of: <!6956>

This was completely broken.

Fixes dEQP-VK.glsl.atomic_operations.add_float32_compute_shared.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <!6936>

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!6936>

Because global operations are lowered before the shader info pass now
we have to adjust the gathering code.

Closes: mesa/mesa#3578
Fixes: 15886445 ("radv: lower deref operations for global memory for both backends")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <mesa/mesa!6934>

Just a cooler name, and a lot easier to search for. thanks Marek
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <!6921>

After disable SDMA on Arcturus(gfx9), dead lock with aux_context_lock is
detected since si_screen_clear_buffer is called recursively before
release lock.

The call trace is:
si_clear_render_target->si_compute_clear_render_target->
si_launch_grid_internal->si_launch_grid->si_emit_cache_flush->
si_prim_discard_signal_next_compute_ib_start->u_suballocator_alloc->
si_resource_create->si_buffer_create->si_alloc_resource->
si_screen_clear_buffer->simple_mtx_lock->
si_sdma_clear_buffer->si_pipe_clear_buffer->
si_clear_buffer->si_compute_do_clear_or_copy->
si_launch_grid_internal->si_launch_grid->si_emit_cache_flush->
si_prim_discard_signal_next_compute_ib_start->u_suballocator_alloc->
si_resource_create->si_buffer_create->si_alloc_resource->
si_screen_clear_buffer->simple_mtx_lock

Fixes: 07a49bf5 "radeonsi: disable SDMA on gfx9"
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <mesa/mesa!6941>

Part-of: <mesa/mesa!6943>

Part-of: <mesa/mesa!6943>

Part-of: <mesa/mesa!6943>