1. 18 Nov, 2020 1 commit
  2. 06 Jul, 2020 1 commit
    • Marcin Ślusarz's avatar
      iris: remove iris_monitor_config · 9f196625
      Marcin Ślusarz authored
      perf_cfg is enough - it already contains almost all necessary
      information and is constructed in a more optimal way (O(n) vs O(n^2)
      - it uses hash table to build the unique counter list).
      
      "Almost all", because it doesn't contain OA raw counters, but
      we should have not exposed them anyway. Quoting Mark Janes:
      "I see no reason to include the OA raw counters in the list that
      are provided to the user. They are unusable.
      The MDAPI library can be used to configure raw counters in a way
      that provides esoteric metrics, but that library is written against
      INTEL_performance_query."
      Signed-off-by: Marcin Ślusarz's avatarMarcin Ślusarz <marcin.slusarz@intel.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: Mark Janes's avatarMark Janes <mark.a.janes@intel.com>
      Part-of: <!5399>
      9f196625
  3. 04 Jun, 2020 1 commit
  4. 03 Jun, 2020 3 commits
    • Francisco Jerez's avatar
      iris: Drop redundant iris_address::write flag. · ae88e79f
      Francisco Jerez authored
      The write flag is redundant since it can be inferred easily from the
      iris_address::access domain.  This allows the iris_address struct to
      be laid out more efficiently in memory, leading to a measurable
      improvement in several Piglit Drawoverhead test-cases.
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Part-of: <!3875>
      ae88e79f
    • Francisco Jerez's avatar
      iris: Annotate all BO uses with domain and sequence number information. · eb5d1c27
      Francisco Jerez authored
      Probably the most annoying patch to review from the whole series --
      Mark every buffer object use as accessed through some caching domain
      with the sequence number of the current synchronization section of the
      batch.  The additional argument of iris_use_pinned_bo() makes sure I'd
      have gotten a compile error if I had missed any buffer added to the
      batch validation list.
      
      There are only a few exceptions where a buffer is left untracked while
      adding it to the validation list, justified below:
      
       - Batch buffers: These are strictly read-only for the moment.
      
       - BLORP buffer objects: Their seqnos are bumped manually at the end
         of iris_blorp_exec() instead, in order to avoid plumbing domain
         information through BLORP address combining.
      
       - Scratch buffers: The contents of these are strictly thread-local.
      
       - Shader images and SSBOs: Accesses of these buffers are explicitly
         synchronized at the API level.
      
      v2: Opt out of tracking more aggressively (Ken): In addition to the
          above, surface states, binding tables, instructions and most
          dynamic states are now left untracked, which means a *lot* more BO
          uses marked IRIS_DOMAIN_NONE which need to be reviewed extremely
          carefully, since the cache tracker won't be able to provide any
          coherency guarantees for them.
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Part-of: <!3875>
      eb5d1c27
    • Francisco Jerez's avatar
      iris: Add infrastructure to partition batch into sync boundaries. · 8cbe9535
      Francisco Jerez authored
      This introduces some minimalistic infrastructure which will be used in
      order to partition the batch into a series of sections, each one with
      a unique, monotonically-increasing sequence number.  Section
      boundaries will typically lie at points in the batch where the
      execution and memory coherency status of some previous commands are
      known, e.g. at batch buffer boundaries or PIPE_CONTROL commands.
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Part-of: <!3875>
      8cbe9535
  5. 28 May, 2020 1 commit
  6. 20 May, 2020 2 commits
  7. 13 May, 2020 1 commit
  8. 01 May, 2020 2 commits
  9. 29 Apr, 2020 1 commit
  10. 11 Apr, 2020 2 commits
  11. 31 Jan, 2020 1 commit
  12. 09 Sep, 2019 1 commit
  13. 07 Sep, 2019 1 commit
  14. 10 Aug, 2019 1 commit
  15. 23 Jul, 2019 1 commit
  16. 21 May, 2019 1 commit
  17. 08 May, 2019 1 commit
  18. 22 Apr, 2019 2 commits
  19. 10 Apr, 2019 1 commit
  20. 08 Mar, 2019 1 commit
    • Kenneth Graunke's avatar
      iris: Use copy_region and staging resources to avoid transfer stalls · 9d1334d2
      Kenneth Graunke authored
      This is similar to intel_miptree_map_blit and intel_buffer_object.c's
      temporary blits in i965.
      
      Improves performance of DiRT Rally by 20-25% by eliminating stalls.
      
      Breaks piglit's spec/arb_shader_image_load_store/host-mem-barrier,
      by using the GPU to do uploads, exposing a st/mesa issue where it
      doesn't give us memory_barrier() calls.  This is a pre-existing issue
      and will be fixed by a later patch (currently out for review).
      9d1334d2
  21. 21 Feb, 2019 9 commits
  22. 19 Dec, 2018 1 commit
  23. 28 Aug, 2018 2 commits
  24. 05 Oct, 2016 1 commit
  25. 01 Feb, 2016 1 commit