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V3D has a bit to set the line caps to be perpendicular to the line
rather than aligned to the edges of the framebuffer. I don’t know what
the disadvantages are of enabling this, but I noticed by experimentation
that enabling line smoothing on the Intel driver also enables nicer line
caps, so it seems nice to enable it here too.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <!5624>

When line smoothing is enabled, the driver now increases the width of
the line so that it can add some semi-transparent pixels to either side
of the line. A lowering pass is added which modifies the alpha component
of every write to fragment output 0 so that if the fragment is outside
the width of the line then the alpha is reduced. It additionally
discards fragments that are completely invisible. It might seem bad to
use discard on a tiled renderer but the assumption is that any bad
effects from using discard will also happen anyway because of enabling
alpha blending.

v2: Disable the line smoothing pass entirely when the framebuffer
    contains an integer colour output or one with no alpha channel.
    Calculate the coverage once upfront and store in a global variable
    instead of calculating each time an output write is modified. Also
    do the conditional discard once upfront.
v3: Don’t check whether the output buffer has an alpha channel. Only
    look at output 0. Use aa_line_width intrinsic instead of calculating
    the real line width in the shader. Clamp the coverage as part of the
    global variable, not per output write.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <!5624>

Adds new QUNIFORMs to store the line widths.

v2: Also handle the aa_line_width intrinsic
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <!5624>

The first intrinsic is intended to expose the value set by glLineWidth
to shaders internally. The second intrinsic exposes the value actually
sent to the hardware. This may be wider than the first one in order to
implement anti-aliasing. These will be used in later patches to
implement a line smoothing lowering pass.

v2: Add a second intrinsic for the expanded line width for
    anti-aliasing.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <!5624>

The line coord intrinsic is loaded from the implicit varying stored in
the same slot as the point coord when drawing lines.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <!5624>

The line coord is a coordinate along the axis perpendicular to the line.
It is in the range [0,1] between the two edges of the line. It is
available at least on Broadcom hardware.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <!5624>

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <!5399>

perf_cfg is enough - it already contains almost all necessary
information and is constructed in a more optimal way (O(n) vs O(n^2)
- it uses hash table to build the unique counter list).

"Almost all", because it doesn't contain OA raw counters, but
we should have not exposed them anyway. Quoting Mark Janes:
"I see no reason to include the OA raw counters in the list that
are provided to the user. They are unusable.
The MDAPI library can be used to configure raw counters in a way
that provides esoteric metrics, but that library is written against
INTEL_performance_query."
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <!5399>

This is necessary now that the compiler respects centroid interpolation,
even in non-MSAA mode. Otherwise the interpolation doesn't work. Fixes a
bunch of dEQP centroid transform feedback tests.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5778>

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

No drivers are using this anymore so we can delete it and not keep
maintaining this legacy code-path.  If any drivers want this in the
future, they should use nir_lower_varst_to_explicit_types followed by
nir_lower_explicit_io.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Gallium drivers should never see nir_var_uniform because gallium lowers
regular uniforms to a UBO.  No GL driver should ever see either
nir_var_mem_shared because that's lowered in GLSL IR.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <!5418>

Both vertex and fragment shaders need to have the lowering.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5751>

As we do not support stream output buffers we only count the primitives
processed by the pipeline. Use the correct query type.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <!5754>

For some reason, in order to get all tests to pass, pretty much all
hardware (across vendors) has to program in offset_units * 2. This fixes
dEQP-GLES3.functional.polygon_offset.float32_displacement_with_units.

While we're at it, add polygon offset clamp support.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5763>

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5753>

For turnip, we use the "bindless" model on a6xx. Loads and stores with
the bindless model require a bindless base, which is an immediate field
in the instruction that selects between 5 different 64-bit "bindless
base registers", a 32-bit descriptor index that's added to the base, and
the usual 32-bit offset. The bindless base usually, but not always,
corresponds to the Vulkan descriptor set.  We can handle the case where
the base is non-constant by using a bunch of if-statements, to make it a
little easier in core NIR, and this seems to be what Qualcomm's driver
does too. Therefore, the pointer format we need to use in NIR has a vec2
index, for the bindless base and descriptor index. Plumb this format
through core NIR.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <!5683>

Add the possibility to specify the source components. This is necessary
to let the UBO/SSBO index have more than one component, and it also lets
us remove a few hand-rolled load intrinsic definitions.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <!5683>

Document this new a6xx_state_src value seen in A640/A650 tess traces.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <!5760>

Avoid inadvertantly becoming master if fdperf happens to be the first
thing to open the device.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5762>

Previously we would match the start of the compatible string, in
a couple of cases, in order to match compatible strings like
"qcom,adreno-630.2".  But these cases would always list a more
generic compatible (ie. "qcom,adreno") as a later choice.  So if
we parse all the compatible strings, we can do a more precise
exact match.

This avoids us accidentially matching on "qcom,adreno-smmu" and
the hilarity that ensues.

Fixes: 5a135071 ("freedreno/perfcntrs: add fdperf")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5762>

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <!5762>

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!5672>

This was causing vkAcquireNextImageKHR to not signal the fences and
semaphores.  In the case where the semaphore was brand new, this could
cause an unsignalled syncobj to be passed into execbuffer2 which it will
reject with -EINVAL leading to VK_ERROR_DEVICE_LOST.  Thanks to Henrik
Rydgård who works on the PPSSPP project for helping me figure this out.

Fixes: ca3cfbf6 "vk: Add an initial implementation of the actual..."
Fixes: 778b51f4 "vulkan/wsi: Add a hooks for signaling semaphores..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!5672>

This reverts commit 7a5e6fd2.

Since we have two different users bisecting issues to this commit, let's
revert.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 7a5e6fd2 "radv: add support for MRTs compaction to avoid holes"
Closes: #3202
Closes: #3228
(Other report in #3151 (comment 558589))

Part-of: <!5758>

We have an issue with early depth testing and discard, where
non-perfect counts count the tile if the early depth test succeeds.

We could spend a lot of effort to set this conditionally based
on the presence of the two conditions, but in the presence of
inherited queries let's try this first.

Changing PERFECT_ZPASS_COUNTS since I'm pretty sure this has a lower
performance impact than always using late depth testing.

CC: <mesa-stable@lists.freedesktop.org>
Closes: #3218Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <!5757>

Seems like we forgot to set it all this time ...

Fixes: b1444c9c "radv: Implement VK_ANDROID_native_buffer."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <!5759>

Fixes: 96063100 "radv: enable shaderStorageImageMultisample feature on GFX8+"
Closes: #3219
Closes: #855Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <!3165>

This reverts commit d2d4677b.

The option is not used by any driver.

Part-of: <!5744>

This reverts commit d2df0761.

The option is not used by any driver.

Part-of: <!5744>

The previous version assumes tess level outputs will only be written once
in the shader, however its not possible to guarantee that.

It also assumes all invocations will write all the levels, which is also
not guaranteed.

This is required to fix the "tesselation" and "terraintessellation" demos
with turnip.

The comment about nir_lower_io_to_temporaries in lower_tess_ctrl_block is
removed because nir_lower_io_to_temporaries specifically skips TESS_CTRL
shaders so the comment doesn't make sense.

The split load for tess levels workaround is removed, the new version only
has scalar access unless if ever gets vectorized.

This sets NIR_COMPACT_ARRAYS cap to avoid the glsl tess vec lowering with
gallium. It seems this will also disable "LowerCombinedClipCullDistance",
which I'm not sure was needed or not.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <!5744>

Accidentally broke this when rebasing the offending commit.

My use case with non-zero explicit offset is UV plane of UBWC NV12, and
only the UBWC slice offset is used for the UBWC sampler, so I didn't catch
it immediately.

Fixes: d53dc6c3 ("freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <!5761>

Clashes with the SI definition.

Closes: #3116Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <!5673>

glGetPerfMonitorCounterInfoAMD(..., ..., GL_COUNTER_RANGE_AMD, ...)
returned NAN (binary representation of uint64_t(-1) as float) as
a max value.

Fixes: 0fd43597 ("iris/perf: implement routines to return counter info")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <mesa/mesa!5473>