1. 19 Oct, 2020 2 commits
    • Kenneth Graunke's avatar
      isl, anv, iris: Add a centralized helper to select MOCS based on usage · 02fe825a
      Kenneth Graunke authored
      
      
      On Gen12+, we can enable additional caches in certain usage situations.
      This routes that decision making to a central place in ISL, based on
      surface usage flags, and updates both drivers to use it.  (i965 doesn't
      need to change because it doesn't support Gen12.)
      
      We continue handling the "external" decision via an anv_mocs() wrapper
      for now, since we store that flag in anv_bo, which isl doesn't know
      about.  (We could introduce an ISL_SURF_USAGE_EXTERNAL, but I'm not
      actually sure that would be cleaner.)
      
      This patch should not have any functional nor performance effects, as
      we continue selecting the exact same MOCS values for now.
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Part-of: <!7104>
      02fe825a
    • Kenneth Graunke's avatar
      anv: Set only one ISL usage bit (RT/texture) for CopyBuffer sources · 103ad427
      Kenneth Graunke authored
      
      
      Most uses of this function deal with destination buffers, but for
      copy_buffer_to_image, the buffer is the source, and isn't rendered
      to.  We should avoid setting ISL_SURF_USAGE_RENDER_TARGET_BIT.
      Also, we should avoid setting ISL_SURF_USAGE_TEXTURE_BIT for the
      destination, which isn't sampled from.
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      Part-of: <!7104>
      103ad427
  2. 15 Oct, 2020 1 commit
    • Ian Romanick's avatar
      anv: Don't generate Gen10-specific functions · fc04733f
      Ian Romanick authored
      v2: Re-wrap lines in meson.build.  Suggested by Jason.
      
      v3: Also update Makefile.sources and Android build files.  Noticed by
      Lionel.
      
      Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
      Part-of: <!6899>
      fc04733f
  3. 22 Sep, 2020 1 commit
  4. 02 Sep, 2020 1 commit
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  7. 17 Mar, 2020 1 commit
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  11. 24 Jan, 2020 2 commits
  12. 20 Jan, 2020 3 commits
  13. 04 Jan, 2020 1 commit
  14. 12 Nov, 2019 1 commit
  15. 31 Oct, 2019 1 commit
  16. 28 Oct, 2019 1 commit
  17. 06 Sep, 2019 1 commit
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  19. 12 Aug, 2019 1 commit
  20. 15 Jul, 2019 1 commit
  21. 19 Jun, 2019 1 commit
    • Jason Ekstrand's avatar
      anv: Flush caches in anv_image_copy_to_shadow · 215f9f83
      Jason Ekstrand authored
      Copies to a shadow image happen during a VkCmdPipelineBarrier or at
      subpass transitions.  We could potentially be a bit more conservative
      but these transitions shouldn't happen often and it's better to have our
      bases covered.
      
      Fixes: f3ea0cf8 "anv: Add stencil texturing support for gen7"
      215f9f83
  22. 17 Jun, 2019 2 commits
  23. 14 Feb, 2019 1 commit
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  27. 19 Jan, 2019 1 commit
  28. 18 Jan, 2019 1 commit
    • Danylo Piliaiev's avatar
      anv: Implement VK_EXT_conditional_rendering for gen 7.5+ · 1952fd8d
      Danylo Piliaiev authored
      
      
      Conditional rendering affects next functions:
      - vkCmdDraw, vkCmdDrawIndexed, vkCmdDrawIndirect, vkCmdDrawIndexedIndirect
      - vkCmdDrawIndirectCountKHR, vkCmdDrawIndexedIndirectCountKHR
      - vkCmdDispatch, vkCmdDispatchIndirect, vkCmdDispatchBase
      - vkCmdClearAttachments
      
      Value from conditional buffer is cached into designated register,
      MI_PREDICATE is emitted every time conditional rendering is enabled
      and command requires it.
      
      v2: by Jason Ekstrand
        - Use vk_find_struct_const instead of manually looping
        - Move draw count loading to prepare function
        - Zero the top 32-bits of MI_ALU_REG15
      
      v3: Apply pipeline flush before accessing conditional buffer
       (The issue was found by Samuel Iglesias)
      
      v4: - Remove support of Haswell due to possible hardware bug
          - Made TMP_REG_PREDICATE and TMP_REG_DRAW_COUNT defines to
             define registers in one place.
      
      v5: thanks to Jason Ekstrand and Lionel Landwerlin
          - Workaround the fact that MI_PREDICATE_RESULT is not
            accessible on Haswell by manually calculating
            MI_PREDICATE_RESULT and re-emitting MI_PREDICATE
            when necessary.
      
      v6: suggested by Lionel Landwerlin
          - Instead of calculating the result of predicate once - re-emit
            MI_PREDICATE to make it easier to investigate error states.
      
      v7: suggested by Jason
          - Make anv_pipe_invalidate_bits_for_access_flag add CS_STALL
            if VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT is set.
      
      v8: suggested by Lionel
          - Precompute conditional predicate's result to
            support secondary command buffers.
          - Make prepare_for_draw_count_predicate more readable.
      Signed-off-by: Danylo Piliaiev's avatarDanylo Piliaiev <danylo.piliaiev@globallogic.com>
      Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason@jlekstrand.net>
      1952fd8d
  29. 17 Jan, 2019 2 commits
  30. 14 Jan, 2019 3 commits
  31. 11 Jan, 2019 1 commit