Commit fe14dc98 authored by Matt Turner's avatar Matt Turner Committed by Marge Bot

intel/compiler: Add assert that set bits are within mask

We generate bitfields of bits that we want to retain (mask) and bits
that we want to set (brw_mode) in the cr0 register, so the bits we want
to set should be in the set of bits we want to retain.

Also, remove the initialization of mask from
fs_visitor::emit_shader_float_controls_execution_mode since
brw_rnd_mode_from_nir initializes the mask parameter unconditionally.
Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!5566>
parent 29e2a3b8
......@@ -242,6 +242,9 @@ brw_rnd_mode_from_nir(unsigned mode, unsigned *mask)
if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE)
*mask |= BRW_CR0_FP_MODE_MASK;
if (*mask != 0)
assert((*mask & brw_mode) == brw_mode);
return brw_mode;
}
......@@ -253,8 +256,8 @@ fs_visitor::emit_shader_float_controls_execution_mode()
return;
fs_builder abld = bld.annotate("shader floats control execution mode");
unsigned mask = 0;
unsigned mode = brw_rnd_mode_from_nir(execution_mode, &mask);
unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask);
abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(),
brw_imm_d(mode), brw_imm_d(mask));
}
......
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