Commit fda76837 authored by Marek Olšák's avatar Marek Olšák

gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsi

parent daa19363
......@@ -51,6 +51,7 @@ Note: some of the new features are only available with certain drivers.
</p>
<ul>
<li>GL_AMD_depth_clamp_separate on r600, radeonsi.</li>
<li>GL_AMD_framebuffer_multisample_advanced on radeonsi.</li>
<li>GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.</li>
<li>GL_AMD_multi_draw_indirect on all GL 4.x drivers.</li>
......
......@@ -69,6 +69,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
......
......@@ -69,6 +69,10 @@ The integer capabilities:
property FS_COORD_PIXEL_CENTER with value INTEGER is supported.
* ``PIPE_CAP_DEPTH_CLIP_DISABLE``: Whether the driver is capable of disabling
depth clipping (through pipe_rasterizer_state)
* ``PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE``: Whether the driver is capable of
disabling depth clipping (through pipe_rasterizer_state) separately for
the near and far plane. If not, depth_clip_near and depth_clip_far will be
equal.
* ``PIPE_CAP_SHADER_STENCIL_EXPORT``: Whether a stencil reference value can be
written from a fragment shader.
* ``PIPE_CAP_TGSI_INSTANCEID``: Whether TGSI_SEMANTIC_INSTANCEID is supported
......
......@@ -186,6 +186,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
......
......@@ -215,6 +215,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
case PIPE_CAP_SM3:
......
......@@ -211,6 +211,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
/* Unsupported features (boolean caps). */
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
......
......@@ -158,6 +158,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
return 1;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
case PIPE_CAP_PRIMITIVE_RESTART:
return 1;
......
......@@ -109,6 +109,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_PRIMITIVE_RESTART:
return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
/* unsupported */
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_SM3:
case PIPE_CAP_INDEP_BLEND_ENABLE:
......
......@@ -219,6 +219,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return class_3d >= NVA3_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
......
......@@ -281,6 +281,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return class_3d >= NVE4_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
......
......@@ -147,6 +147,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
case PIPE_CAP_TGSI_INSTANCEID:
......
......@@ -493,7 +493,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
rs->pa_cl_clip_cntl =
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
rs->multisample_enable = state->multisample;
......
......@@ -265,6 +265,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
......
......@@ -480,7 +480,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
rs->pa_cl_clip_cntl =
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
if (rctx->b.chip_class == R700) {
rs->pa_cl_clip_cntl |=
......
......@@ -71,6 +71,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
......
......@@ -870,7 +870,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
rs->pa_cl_clip_cntl =
S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_near) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
......
......@@ -144,6 +144,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_CONDITIONAL_RENDER:
return 1;
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: /* draw module */
......
......@@ -283,6 +283,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
return sws->have_vgpu10 ? 140 : 120;
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
case PIPE_CAP_SM3:
......
......@@ -203,6 +203,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
return PIPE_ENDIAN_NATIVE;
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
/* supported features */
......
......@@ -150,6 +150,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
case PIPE_CAP_COMPUTE:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
......
......@@ -668,6 +668,7 @@ enum pipe_cap
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
PIPE_CAP_DEPTH_CLIP_DISABLE,
PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE,
PIPE_CAP_SHADER_STENCIL_EXPORT,
PIPE_CAP_TGSI_INSTANCEID,
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
......
......@@ -743,6 +743,7 @@ void st_init_extensions(struct pipe_screen *screen,
{ o(EXT_transform_feedback), PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS },
{ o(EXT_window_rectangles), PIPE_CAP_MAX_WINDOW_RECTANGLES },
{ o(AMD_depth_clamp_separate), PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE },
{ o(AMD_framebuffer_multisample_advanced), PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS },
{ o(AMD_pinned_memory), PIPE_CAP_RESOURCE_FROM_USER_MEMORY },
{ o(ATI_meminfo), PIPE_CAP_QUERY_MEMORY_INFO },
......
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